8.1.2 Cache Controller and Tightly Coupled Memory (TCM) Interface

The device features two cache controllers with TCM memories. The total cache memory can be used as cache only, or as a mix of cache and TCM RAM.

Important: When used as TCM, SRAM memories embedded in both cache controllers (CMCC0 and CMCC1) are 32-bit accessible memories only. 8-bit or 16-bit accesses are not allowed. The code to load the ITCM during application initialization must use a “32-bit wide” memory copy (memcpy) function.

The CMCC0 is dedicated to Program Code (Instruction Fetch) and CMCC1 is dedicated to Program Data (RO Data, Literal pool). Both cache controllers can be used either for the internal Flash memory or for an external serial memory connected to the QSPI or both.

Cache and tightly-coupled memories allow different run-time memory mapping scenarios using TCM to adapt for “real-time response” and/or increase execution speed from Flash using cache. Both cache and TCM can be used at the same time, and memory size for each can be allocated at build time.

The DTCM accessible only by the core may be used as storage memory for the main stack typically used by the kernel of OS/RTOS. The process stack used by OS/RTOS tasks can be located in SRAM0. This creates a physical separation between the two stacks and, as a result, a safety level is added.