19.6 PLL Controls
The PMC embeds 3 PLLs that are controlled by the registers PMC_PLL_CTRL0, PMC_PLL_CTRL1, PMC_PLL_CTRL2, PMC_PLL_SSR, PMC_PLL_ACR and PMC_PLL_UPDATE.
Although these PLLs are similar, their implementations differ in terms of input clock signal, maximum output clock frequency or availability of a dedicated output line.
Each PLL has a constraint on the frequency it can generate on its clock output. Refer to the section “Electrical Characteristics”.
The table below describes all PLLs with their names and source clocks. For maximum frequency, refer to the section “Electrical Characteristics”.
| Index | PLL Name | Clock Name | PLL Clock Source | Usage Example |
|---|---|---|---|---|
| 0 | PLLA | PLLACK0 | MAINCK/TD_SLOW_CLOCK | See General Clock Distribution Block Diagram |
| PLLACK1 | ||||
| 1 | PLLB | PLLBCK | PLLACK0/MAINCK | |
| 2 | PLLC | PLLCCK | PLLACK0/MAINCK |