19.6.1 Divider and Phase Lock Loop Programming

Each PLL is controlled the same way. The internal clock frequency is configured by setting PMC_PLL_CTRL1.MUL and PMC_PLL_CTRL2.FRACR.

The COREPLLCK operating frequency for PLLA, PLLB and PLLC is defined as:

f COREPLLCK = f ref MUL + 1 + FRACR 2 22

where fref = Selected reference clock in the figure PLL Controls.

PLLACK0, PLLBCK and PLLCCK clock frequencies, noted as fPLL in the formula below, are defined by the following formula:

f PLL = f COREPLLCK DIVPMC 0 + 1

The PLLACK1 frequency is defined by the following formula:


f PLLACK1 = f COREPLLCK DIVPMC 1 + 1

Each PLL sends a lock signal to the PMC to indicate its lock status. Once the lock signal has risen, the clock generated by the PLL is stable and can be sent to the PMC and/or its corresponding I/O if available.

This signal reports the lock status of the PLL by setting the corresponding PMC_PLL_CTRL0.ENLOCK to ‘1’.

If the lock status is disabled, a start-up time can be used instead in the PMC_PLL_UPDT register. The start-up time is expressed as a number of MD_SLCK cycles. Once the counter has reached the specified value, a flag rises. The start-up time field can only be written while all PLLs are disabled (i.e., their PLLEN fields are null).

If both a start-up time and the lock are enabled, the lock sent by the PLL is read once the start-up time has elapsed.

If neither the start-up time nor the lock are enabled, there is no way to know the lock status of the PLL.

The PLL also embeds an unlock status that informs when the PLL lock is lost. When enabled, this status is read once the start-up time (if defined) has elapsed.

The lock and unlock status can be used as interrupts.

Refer to the figure below.

Figure 19-4. PLL Controls

Follow the steps below to initialize and start a PLL:

Note: Steps referring to ENPLLO1 and DIVPMC1 apply to PLLA only.
  1. Define the ID (ID=n) and start-up time by configuring the fields PMC_PLL_UPDT.ID and PMC_PLL_UPDT.STUPTIM. Set PMC_PLL_UPDT.UPDATE to ‘0’.
  2. Configure PMC_PLL_ACR with the following values:
    • PLLA = 0x0F000038
    • PLLB = 0x28000058
    • PLLC = 0x28000058
  3. Define the MUL and FRACR to be applied to PLL(n) in PMC_PLL_CTRL1 and PMC_PLL_CTRL2, respectively.
  4. Set PMC_PLL_UPDT.UPDATE to ‘1’. PMC_PLL_UPDT.ID must equal the one written during Step 1. else the update is cancelled.
  5. In PMC_PLL_CTRL0, write a ‘1’ to ENLOCK and to ENPLL and configure DIVPMC0, DIVPMC1, ENPLLO0 and ENPLLO1.
  6. Set PMC_PLL_UPDT.UPDATE to ‘1’. PMC_PLL_UPDT.ID must equal the one written during Step 1. else the update is cancelled.
  7. Wait for the lock bit to rise by polling the PMC_PLL_ISR0 or by enabling the corresponding interrupt in PMC_PLL_IER.
  8. Disable the interrupt (if enabled)
  9. Enable the unlock interrupt to quickly detect a failure on the generation of the clock of the PLL.

Once enabled (PMC_PLL_CTRL0.ENPLL=1), the PLL core generates its core clock (COREPLLCK).

Once the PLL has been enabled and has locked, the configuration of the PLL can be modified without switching off the cell.

The clock generated by the PLL (COREPLLCK) is sent to the PMC if ENPLLO0 has been set to ‘1’ and PMC_PLL_UPDT.UPDATE has then been written to ‘1’.

The first clock generated by the PLLA is sent to the PLLB and PLLC.

To stop a PLL, the following sequence must be applied:

  1. If the PLL drives a section of the system that is active, modify the source clock of the system.
  2. Define the ID (ID=n) of the PLL to be switched off in PMC_UPDT. Set PMC_UPDT.UPDATE to ‘0’ in this step.
  3. In PMC_PLL_CTRL0, clear ENPLLO0 and leave ENPLL at ‘1’.
  4. Set PMC_PLL_UPDT.UPDATE to ‘1’. PMC_PLL_UPDT.ID must equal the one written during Step 2. else the update is cancelled.
  5. Write a ‘0’ to PMC_PLL_CTRL0.ENPLL.