5.8 Flash Memory Hardware ERASE Signal

A hardware erase is when the ERASE signal on PB2 pin is used to reinitialize the Flash content (memory array), the lock bits, GPNVM bits and security bit to an erased state. After a hardware erase, the memory array bits read as logic level 1, GPNVM bits read as logic level 0 and lock bits are in an unlocked state. The ERASE signal on PB2 pin integrates a pull-down resistor of about 100 kΩ to GND, so that it can be left unconnected for normal operations. The ERASE signal is the default mode on the PB2 pin.

If necessary, the hardware ERASE signal may be partially or permanently disabled by programming the Erase Function Lock (EFL) GPNVM bit [4:2]. Note that the security bit must be set in these cases. Otherwise, regardless of the value of the GPNVM bit [4:2], the ERASE signal will trigger an ERASE sequence if set to logic level high.

Note that it is strongly advised to disable the Erase function using the EFL once the production software has been fully validated. Refer to the GPNVM bit description in the section ROM Code and Boot Strategies for further details and correct use.

The ERASE signal is a system I/O signal that is available in the IO multiplexing. As a result, this pin can also be used as a standard general purpose I/O (GPIO). Configuration of this pin as a GPIO is done through the PIO Controller. Care must be taken when changing this pin between GPIO and peripheral function. Pull-up on this line must be disabled before assigning this pin to its peripheral function (i.e., the ERASE function). At start-up, the system I/O pin defaults to the ERASE function if it has not been disabled.

To avoid unexpected erase at power-up due to glitches, this pin is debounced by SLCK to improve glitch tolerance and minimum ERASE pin assertion time is required. Note that it is also mandatory to not power-down the device once the hardware erase sequence has been started until the hardware erase time has elapsed. Refer to timings in Electrical Characteristics.

If the ERASE signal is used as a standard I/O in Input or Output mode, note the following considerations and behavior:
Note: If the EFL mode has been set to partially or permanently disabled, the recommendations below do not apply.
  • GPIO Input mode—At device start-up, the logic level of the pin must be low to prevent unwanted erasing until the user application has configured this system I/O pin to a standard I/O pin.
  • GPIO Output mode—Asserting the pin to low does not erase the Flash.
  • GPIO Input mode—Pull-up on this pin (PB2) must be disabled before setting this pin in ERASE signal mode.

During software development, faulty software may put the device into a deadlock and prevent the user from recovering the device.

This may be due to:

  • programming an incorrect clock switching sequence
  • using pin PB2 as a standard I/O pin
  • entering Wait mode without any wake-up events programmed

The only way to recover normal behavior is to erase the Flash by following the steps below:

  1. Apply a logic “1” level on the pin PB2 (ERASE signal).
  2. Apply a logic “0” level on the pin NRST.
  3. Power down, then power up the device.
  4. Maintain the pin PB2 (ERASE signal) at logic “0” level for at least the minimum assertion time after releasing the NRST pin to logic “1” level.