30.4.1.2 Interrupt Source Control

Each interrupt source (IRQ0 to IRQ31) can be enabled or disabled by using the command registers Interrupt Enable Command (IPC_IECR) and Interrupt Disable Command (IPC_IDCR). This set of registers conducts enabling or disabling of an instruction. The interrupt mask can be read in the Interrupt Mask register (IPC_IMR). All IPC interrupts can be enabled/disabled, thus configuring IPC_IMR. Each pending and unmasked IPC interrupt asserts the IPC output interrupt line. A disabled interrupt does not affect servicing of other interrupts.