34.9.3.9.2 Data Receive with the PDC in Host Mode

The PDC transfer size must be defined with the buffer size minus 2. The two remaining characters must be managed without PDC to ensure that the exact number of bytes are received regardless of system bus latency conditions during the end of the buffer transfer period.

If Alternative Command mode is disabled (ACMEN bit set = 0):

  1. Initialize the receive PDC (memory pointers, transfer size - 2).
  2. Configure Host mode (DADR, CKDIV, MREAD = 1, etc.).
  3. Set the PDC RXTEN bit.
  4. (Host only) Write the START bit in FLEX_TWI_CR to start the transfer.
  5. Wait for the PDC ENDRX flag either by using polling method or ENDRX interrupt.
  6. Disable the PDC by setting the PDC RXTDIS bit.
  7. Wait for the FLEX_TWI_SR.RXRDY flag.
  8. Set the STOP command in FLEX_TWI_CR to end the transfer.
  9. Read the penultimate character in FLEX_TWI_RHR.
  10. Wait for the FLEX_TWI_SR.RXRDY flag.
  11. Read the last character in FLEX_TWI_RHR.
  12. (Optional) Wait for the FLEX_TWI_SR.TXCOMP flag before disabling the peripheral clock if required.

If Alternative Command mode is enabled (ACMEN bit = 1):

  1. Initialize the transmit PDC (memory pointers, transfer size).
  2. Configure Host mode (DADR, CKDIV, etc.).
  3. Set the PDC RXTEN bit.
  4. (Host only) Write the FLEX_TWI_CR.START bit to start the transfer.
  5. Wait for the PDC ENDTX Flag by using either the polling method or the ENDTX interrupt.
  6. Disable the PDC by setting the PDC TXTDIS bit.
  7. (Optional) Wait for the FLEX_TWI_SR.TXCOMP flag before disabling the peripheral clock if required.