50.3.1 Power Supply Inputs

Table 50-3. Recommended Operating Conditions on Power Supply Inputs
Supply Name	Parameter	Conditions	Min	Max	Unit
VDD3V3	Core voltage regulator input LCD voltage regulator input, Analog block supply (ADC, Temp Sensor and voltage reference) I/O Buffers lines Power Supply Flash memory charge pumps supply for read, erase and program operations	VDD3V3 and VDDIN_AFE are powered from one single power source such that V(VDD3V3,VDDIN_AFE) ≤ 50mV	–	–	V
12-bit ADC, LCD and Internal Voltage Reference not operating	2.25	3.6	V
12-bit ADC operating with external reference voltage. LCD with external supply	2.5	3.6	V
All analog blocks and LCD operating	2.8	3.6	V
VDDCORE	Core Logic Power Supply (including CPU, Memories and Peripherals)	f_CPU0 ≤ 200 MHz, f_MCK0 ≤ 200 MHz, f_MCK0DIV ≤ 100 MHz, f_CPU1 ≤ 240 MHz, f_MCK0DIV2 ≤ 100 MHz f_MCK1 ≤ 240 MHz, f_MCK1DIV ≤ 120 MHz Applies only when VDDCORE and VDDPLL are powered from an external regulator. VDDCORE and VDDPLL are powered from one single power source such that V(VDDCORE,VDDPLL) ≤ 50mV	1.04	1.21	V
VDDPLL	PLLs and 12-48 MHz Crystal Oscillators supply
VBAT	Power supply of the backup area if no VDD3V3	–	1.65	3.6	V
VDDLCD	LCD voltage regulator input or output for the LCD Driver, and its logic	At any time, VDDLCD ≤ VDD3V3	2.5	3.6	V
VDDIN_AFE	VDDA regulator power supply	–	3.0	3.6	V
VDDA	EMAFE analog circuits power supply input	–	2.7	2.9	V
t_{R_VDD}	Power supply slope at power-up	Applies to any of the power supply inputs listed above	0.2	20	mV/μs
t_{F_VDD}	Power supply slope at power-down	Applies to any of the power supply inputs listed above	-20	-1	mV/μs

VDD3V3

Core voltage regulator input
LCD voltage regulator input,
Analog block supply (ADC, Temp Sensor and voltage reference)
I/O Buffers lines Power Supply
Flash memory charge pumps supply for read, erase and program operations

VDD3V3 and VDDIN_AFE are powered from one single power source such that V(VDD3V3,VDDIN_AFE) ≤ 50mV

–

V

12-bit ADC, LCD and Internal Voltage Reference not operating

2.25

3.6

V

12-bit ADC operating with external reference voltage.

LCD with external supply

2.5

3.6

V

All analog blocks and LCD operating

2.8

3.6

V

VDDCORE

Core Logic Power Supply (including CPU, Memories and Peripherals)

f_CPU0 ≤ 200 MHz,
f_MCK0 ≤ 200 MHz,
f_MCK0DIV ≤ 100 MHz,
f_CPU1 ≤ 240 MHz,
f_MCK0DIV2 ≤ 100 MHz
f_MCK1 ≤ 240 MHz,
f_MCK1DIV ≤ 120 MHz

Applies only when VDDCORE and VDDPLL are powered from an external regulator.

VDDCORE and VDDPLL are powered from one single power source such that V(VDDCORE,VDDPLL) ≤ 50mV

1.04

1.21

V

VDDPLL

PLLs and 12-48 MHz Crystal Oscillators supply

VBAT

Power supply of the backup area if no VDD3V3

–

1.65

3.6

V

VDDLCD

LCD voltage regulator input or output for the LCD Driver, and its logic

At any time, VDDLCD ≤ VDD3V3

2.5

3.6

V

VDDIN_AFE

VDDA regulator power supply

–

3.0

3.6

V

VDDA

EMAFE analog circuits power supply input

–

2.7

2.9

V

t_{R_VDD}

Power supply slope at power-up

Applies to any of the power supply inputs listed above

0.2

20

mV/μs

t_{F_VDD}

Power supply slope at power-down

Applies to any of the power supply inputs listed above

-20

-1

mV/μs