50.8.2.1 Flash Wait States and Operating Frequency
The maximum operating frequency given in the following table is limited by the Embedded Flash access time when the processor is fetching code out of it. The table gives the device maximum operating frequency depending on the FWS field of the EFC_FMR register. This field defines the number of wait states required to access the Embedded Flash memory.
| FWS (Flash Wait State) | Core 0 Frequency(1, 2) | Unit |
|---|---|---|
| 0 | 25 | MHz |
| 1 | 51 | |
| 2 | 76 | |
| 3 | 102 | |
| 4 | 127 | |
| 5 | 153 | |
| 6 | 179 | |
| 7 | 204 |
Note:
- Over the full temperature and VDDCORE/VDD3V3 voltage range of the device.
- Simulation data.