38.5.16 Buffer Structure with FIFO

The DMA read channel is triggered when the fields ENFIFO and ENLEVEL are used (see ADC_FMR).

If the configuration ENFIFO is high and ENLEVEL is low, the DMA read channel is triggered as soon as one data is written.

When at least one data is ready in the FIFO, the RXRDY flag rises and remains high as long as there is at least one data to be read in the FIFO. When the entire FIFO has been filled with data, the RXFULL flag rises. If a new data is written into the RX FIFO while RXFULL is high, then the RXOVR flag rises. This flag remains high until ADC_ISR is read.

Once all data contained in the RX FIFO have been read, the RXEMPTY flag rises. If a data is read while the RX FIFO is empty, an underrun occurs and the RXUDR flag rises. This flag remains high until ADC_ISR is read.

Once a data is written in the RX FIFO, the RXRDY flag rises. If the corresponding interrupt has been enabled, an interrupt is generated and remains high as long as a data is available in the RX FIFO.

The DMA read channel is triggered when a new data is stored in FIFO. The same structure of data is repeatedly stored in FIFO each time a trigger event occurs. Depending on the user mode of operation (ADC_MR, ADC_CHSR, ADC_SEQR1, ADC_TSMR), the structure differs. Each data read to DMA buffer, carried on a half-word (16 bits), consists of last converted data right-aligned, and when ADC_EMR.TAG is set, the four most significant bits carry the channel number, thus allowing an easier post-processing in the DMA buffer or a better checking of the DMA buffer integrity.

ADC_FMR.FIFOCNT gives the number of conversions available in the FIFO.