2.3 SCK

When programming the AVR in Serial mode, the In-System Programmer supplies clock information on the SCK pin. This pin is always driven by the programmer, and the target system should never attempt to drive this wire when target reset is active. Immediately after the Reset goes active, this pin will be driven to zero by the programmer. During this first phase of the programming cycle, keeping the SCK Line free from pulses is critical, as pulses will cause the target AVR to lose synchronization with the programmer. When in synchronization, the second byte ($53), will echo back when issuing the third byte of the programming enable instruction. If the $53 did not echo back, give Reset a positive pulse, and issue a new Programming Enable command.

The target AVR microcontroller will always set up its SCK pin to be an input with no pull-up whenever Reset is active. See also the description of the Reset wire.

The minimum low and high periods for the Serial Clock (SCK) input are defined in the programming section of the datasheet. For the AT90S1200 they are defined as follows:

Low: >1 XTAL1 clock cycle

High: >4 XTAL1 clock cycles