3.2 Advanced Options and Strategies

[-str ifmt TT | edif] Input Netlist File Format (FIT15XX only)

[-str lib] Library File Name for EDIF Input (FIT15XX only)

This option allows the user to specify the path and file name of the ATF15xx library file (APRIM.LIB) required for the EDIF netlist. The command

[-str MC_power OFF | on = node_name1, node_name2, ...] Macrocell Reduced Power Mode (FIT15XX only)

This option allows the user to enable or disable the Macrocell Reduced Power feature and to specify the macrocells to which it applies. When enabled, macrocell power consumption is reduced by approximately 50%. The command

[-str MC_power OFF | on = node_name1, node_name2, ...] Macrocell Reduced Power Mode (FIT15XX only)

[-str open_collector OFF | on = pin_name1, pin_name2, ...] Open Collector Output (FIT15XX only)

This option allows users to enable or disable the open-collector output feature and to specify the output pins to which it applies.

[-str power_reset OFF | on] Power-up Reset Hysteresis (FIT15XX only)

This option allows the user to control the power reset hysteresis feature in the ATF15XX devices. When this option is set to off, the power-up reset hysteresis in the ATF15XX will be set to small. When this option is set to on, the power-up reset hysteresis in the ATF15XX will be set to large. The command

[-strJTAG off | ON] JTAG Port (FIT15XX only)

This option allows users to control the JTAG port feature in the ATF15XX. The command

[-str TDI_pullup OFF | on] Internal Pull-up Resistor on TDI Pin (FIT15XX only)

This option controls the internal pull-up resistor feature on the JTAG TDI pin. When set to on, the internal pull-up resistor on the TDI pin will be enabled. The JTAG port feature must be enabled when the internal pull-up resistor on the TDI pin is enabled. The command

[-str ues value] User Electronic Signature (FIT15XX only)

This option allows users to specify the value for the 16-bit User Electronic Signature (UES) to be programmed into the ATF15XX as 2 ASCII characters. The command

[-str no_tff OFF | on] Do Not Use T Flip-flop (FIT15XX only)

This options prevents the fitter from using T flip-flops during logic implementation. This feature is available only for ATF15xxBE designs. The command

[-str tPD 5 | 7 | 10 | 15 | 20 | 25 ] Logic Optimization (FIT15XX only)

This options allows users to specify the speed grade of the target device. The post-fit timing simulation files generated by the fitter are based on the selected tPD value. The command

[-str voltage_level_A 1.8 | 2.5 | 3.3] Voltage Level for I/O Bank A (FIT15XX only)

This option allows users to specify the voltage level for I/O Bank A of the target device. Post-fit timing simulation files are generated based on the specified voltage level. This option is available only for ATF15xxBE designs. The command

[-str voltage_level_B 1.8 | 2.5 | 3.3] Voltage Level for I/O Bank B (FIT15XX only)

This option allows users to specify the voltage level for I/O Bank B of the target device. Post-fit timing simulation files are generated based on the specified voltage level. This option is available only for ATF15xxBE designs. The command

[-str fast_inlatch OFF | on = pin_name1, pin_name2, ...] Direct I/O Input (FIT15XX only)

This option instructs the fitter to attempt to use direct I/O inputs for the data input of flip-flops or latches, where possible. The command

[-str schmitt_trigger OFF | on = pin_name1, pin_name2, ...] Schmitt Trigger Input (FIT15XX only)

This option allows users to enable or disable the Schmitt Trigger input feature and to specify the input pins to which it applies. This feature is available only for ATF15xxBE designs. The command

[-str pull_up OFF | on = pin_name1, pin_name2, ...] Pin Pull-up Resistor (FIT15XX only)

This option allows users to enable or disable the internal pull-up resistor and to specify the input or I/O pins to which it applies. This feature is available only for ATF15xxBE designs. The command

[-str unused_To_PinKeeper off | ON] Pin-keeper for Unused Pins (FIT15XX only)

This option allows users enable or disable the Pin-Keeper feature for unused input and I/O pins. This feature is available only for ATF15xxBE designs. The command

[-str pull_up_unused OFF | on] Pull-up for Unused Pins

This option allows users to enable or disable internal pull-up resistors for unused input and I/O pins. This feature is available only for ATF15xxBE designs. The command

[-str unused_To_Ground OFF | on] Set Unused Pins to Ground

This option allows users to configure unused input and I/O pins as additional ground pins. This feature is available only for ATF15xxBE designs. The command

[-str pull_down OFF = pin_name1, pin_name2, ...] Pin Pull-Down Resistor (FIT15XX only)

This option allows users to enable or disable the internal pull‑down resistor and to specify the input or I/O pins to which it applies. This feature is available only for ATF15xxBE designs. The command

[-str GCLK_ITD AUTO | on | off | GCLK1 | GCLK2 | GCLK3] Input Transition Detection for GCLK1/2/3 (FIT15XX only)

This option allows users to enable or disable the input transition detection feature and to specify the GCLK pin to which it applies. This feature is available only for ATF15xxASL/ASVL designs. The command

[-str Latch_Synthesis ON | off] Latch Synthesis (FIT15XX only)

This option controls whether the fitter attempts to implement latches using logic gates. The command

[-str optimize ON | off] Logic Optimization (FIT1500 and FIT15XX)

This options allows the user to control all of the fitter’s logic optimization strategies. These strategies include Cascade and Foldback logic, XOR Synthesis and Node Collapsing. Logic optimization is enabled by default. The command

[-str cascade_logic ON | Off = signal_name,..., signal_name] Cascade Logic (FIT1500 and FIT15XX)

This option allows users to control the use of cascade logic in ATF15xx/ATF1500 macrocells for implementing logic functions. This option can be enabled for either all output signals or for individual signals that are listed. These signals can represent either pins or nodes in the design. The cascade logic feature allows the user to borrow product terms from an adjacent macrocell with a small additional delay. This feature is useful for implementing high product term fan-in designs such as state machines or for optimizing a design for speed. This option is enabled by default. The command

[-str foldback_logic ON | Off = signal_name,...,signal_name] Foldback Logic (FIT1500 and FIT15XX)

This option allows users to control whether foldback logic nodes are used in the ATF15XX/ATF1500 macrocells. This option can be enabled for all signals or limited to specific signals, which represent nodes in the design. This feature is useful for fitting additional logic into a macrocell when making design upgrades or modifications. Foldback logic is enabled by default. The command

[-strategy expander = node_name,...,node_name] Sharable Expander Logic (FIT1500 only)

This option allows users to define sharable expander logic equations in ATF1500 designs. It can be applied to all signals or to specific signals, which represent nodes in the design. When enabled, sharable expander logic equations are automatically converted to foldback logic nodes. Sharable expander logic equations include an implicit inversion. In contrast, foldback logic nodes in ATF1500 designs require the inversion be defined in the logic equations. For example,

[-strategy soft_buffer OFF | On = node_name,...,node_name] Node Collapsing (FIT1500 and FIT15XX)

This option allows users to prevent specific nodes from being collapsed by the fitter. By default, the fitter allows all nodes to be collapsed. This strategy can be enabled for either all signals or for individual signals. These signals represent nodes in the design. Preventing certain nodes from collapsing can help a design fit into the ATF15XX or ATF1500 devices. Please refer to the Hint 6 - Prevent Certain Nodes from Collapsing for more information about how to use the node collapsing feature. This option is disabled by default. The command

[-str xor_synthesis ON | Off = signal_name,…,signal_name] XOR Synthesis (FIT1500 and FIT15XX)

This option allows users to control the use of the hardware XOR gate in ATF15xx/ATF1500 macrocells for logic synthesis. XOR synthesis can be enabled for all output signals or limited to specific signals, which may represent either pins or internal nodes. The hardware XOR gate is effective in reducing product‑term usage for arithmetic logic, comparison functions and other XOR‑based logic. When this option is enabled, the fitter uses the hardware XOR gate only if it produces fewer product terms than an equivalent non‑XOR implementation. This option is enabled by default. The command

[-strategy dedicated_input ON | Off = pin_name,...,pin_name] Dedicated Inputs (FIT1500 only)

This option instructs the fitter to place selected input signals on the dedicated input pins of the ATF1500 device. Up to four input signals may be assigned, depending on the availability of global resources such as pin clocks, output enables, and reset signals. If dedicated inputs are explicitly defined in the design source file, those assignments override this option. This feature is enabled by default. The command

[-str output_fast On | OFF = pin_name,...,pin_name] Slew Rate Control (FIT1500 and FIT15XX)

This option allows the user to define the output slew rate for ATF15xx and ATF1500 devices. The slew rate can be defined as either fast or slow. The option may be applied to all output pins or limited to specific pins. By default, all outputs are configured for a slow slew rate, and this option is disabled. The command

[-str pd1=on] [-str pd2=on] [-str sleep] Power-Down Control (FIT1500 and FIT15XX)

This option enables use of the power-down pin on ATF15xx and ATF1500 devices. This pin powers down the device to a zero-power mode. ATF15XX devices provide two such pins (PD1 or PD2), to enable this mode. ATF1500 devices use the SLEEP option for power‑down control. When this feature is enabled, the macrocell associated with the PD pin is available for buried logic functions such as foldback or cascade logic. This option is disabled by default.

[-str jedec_file = file_name] JEDEC File (FIT1500 only)

This option allows users to specify a custom file name or directory for the generated JEDEC (.JED) file. By default, the fitter creates a JEDEC file using the design name and saves it in the working directory.

[-str vector_file = file_name] Vector File (FIT1500 only)

This option allows users to append a custom set of test vectors to the JEDEC file generated by the fitter. The vector file may be specified using a custom file name or directory. By default, the fitter reads a [.tmv] file from the working directory. The command

[-str security OFF | on] Read Security (FIT1500 and FIT15XX)

This option controls the Read Security feature of ATF15xx and ATF1500 devices. When enabled, the device contents cannot be read back after programming. Disabling the Read Security feature requires a complete device erase. The command

[-str pin_keep OFF | on] Pin-Keeper Circuits (FIT1500 and FIT15XX)

This option allows the user to enable or disable the Pin-Keeper feature, which maintains the last known logic on an input or I/O pin when it is not actively driven. The command

[-str Verilog_sim sdf | Verilog | OFF] Verilog Simulation Output Files (FIT15XX only)

This option allows the user to specify whether the Verilog timing simulation files should be generated or not. This includes the standard delay format (SDF) output and Verilog netlist output files. The command

[-str Vhdl_sim sdf | vhdl | OFF] VHDL Simulation Output Files (FIT15XX only)

This option allows the user to specify whether the VHDL timing simulation files should be generated or not. This includes the standard delay format (SDF) output and VHDL netlist output files. The command

[-str Out_Edif on | OFF] EDIF Netlist Output File (FIT15XX only)

This option allows the user to specify whether the EDIF netlist output file should be generated or not. The command

[-str logic_doubling on | OFF] Logic Doubling (FIT15XX only)

This option allows the user to specify whether the fitter should try to use the Logic Doubling features in the ATF15xx or not. The command