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24.8.4 CLCnSEL0 Generic CLCn Data 1 Select
Register Name: CLCnSEL0 Address: 0x0D8
Bit 7 6 5 4 3 2 1 0 D1S[5:0] Access R/W R/W R/W R/W R/W R/W Reset x x x x x x
Bits 5:0 – D1S[5:0] CLCn Data1 Input Selection
Table 24-2. CLC Input Selection
DyS
Input Source
DyS (cont.)
Input Source (cont.)
DyS (cont.)
Input Source (cont.)
[0] 0000 0000
CLCIN0PPS
[22] 0001 0110
TMR4
[44] 0010 1100
CLC6
[1] 0000 0001
CLCIN1PPS
[23] 0001 0111
TMR6
[45] 0010 1101
CLC7
[2] 0000 0010
CLCIN2PPS
[24] 0001 1000
CCP1
[46] 0010 1110
CLC8
[3] 0000 0011
CLCIN3PPS
[25] 0001 1001
CCP2
[47] 0010 1111
U1TX
[4] 0000 0100
CLCIN4PPS
[26] 0001 1010
PWM1S1P1_OUT
[48] 0011 0000
U2TX
[5] 0000 0101
CLCIN5PPS
[27] 0001 1011
PWM1S1P2_OUT
[49] 0011 0001
SPI1_SDO
[6] 0000 0110
CLCIN6PPS
[28] 0001 1100
PWM2S1P1_OUT
[50] 0011 0010
SPI1_SCK
[7] 0000 0111
CLCIN7PPS
[29] 0001 1101
PWM2S1P2_OUT
[51] 0011 0011
SPI1_SS
[8] 0000 1000
FOSC
[30] 0001 1110
PWM3S1P1_OUT
[52] 0011 0100
SPI2_SDO
[9] 0000 1001
HFINTOSC(1 )
[31] 0001 1111
PWM3S1P2_OUT
[53] 0011 0101
SPI2_SCK
[10] 0000 1010
LFINTOSC(1 )
[32] 0010 0000
NCO1
[54] 0011 0110
SPI2_SS
[11] 0000 1011
MFINTOSC(1 )
[33] 0010 0001
CMP1_OUT
[55] 0011 0111
I2 C1_SCL
[12] 0000 1100
MFINTOSC (31.25 kHz)(1 )
[34] 0010 0010
CMP2_OUT
[56] 0011 1000
I2 C1_SDA
[13] 0000 1101
SFINTOSC (1 MHz)(1 )
[35] 0010 0011
ZCD1
[57] 0011 1001
I2 C2_SCL
[14] 0000 1110
SOSC(1 )
[36] 0010 0100
ZCD2
[58] 0011 1010
I2 C2_SDA
[15] 0000 1111
EXTOSC(1 )
[37] 0010 0101
IOC
[59] 0011 1011
CWG1A
[16] 0001 0000
ADCRC(1 )
[38] 0010 0110
HLVD_OUT
[60] 0011 1100
CWG1B
[17] 0001 0001
CLKR
[39] 0010 0111
CLC1
[61] 0011 1101
TU16A
[18] 0001 0010
TMR0
[40] 0010 1000
CLC2
[62] 0011 1110
TU16B
[19] 0001 0011
TMR1
[41] 0010 1001
CLC3
[63] 0011 1111
PORTW IOC
[20] 0001 0100
TMR2
[42] 0010 1010
CLC4
[64] 0100 0000
-
[21] 0001 0101
TMR3
[43] 0010 1011
CLC5
[65] 0100 0001
-
Reset States: POR/BOR = xxxxxx All Other Resets = uuuuuu
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