24.8.10 CLCnGLS2

CLCn Gate3 Logic Select Register
Name: CLCnGLS2
Address: 0x0DE

Bit 76543210 
 G3D4TG3D4NG3D3TG3D3NG3D2TG3D2NG3D1TG3D1N 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset xxxxxxxx 

Bits 1, 3, 5, 7 – G3DyT dyT: Gate3 Data ‘y’ True (noninverted)

Reset States: 
POR/BOR = xxxx
All Other Resets = uuuu
ValueDescription
1 dyT is gated into g3
0 dyT is not gated into g3

Bits 0, 2, 4, 6 – G3DyN dyN: Gate3 Data ‘y’ Negated (inverted)

Reset States: 
POR/BOR = xxxx
All Other Resets = uuuu
ValueDescription
1 dyN is gated into g3
0 dyN is not gated into g3