24.8.2 CLCnCON
| Name: | CLCnCON |
| Address: | 0x0D6 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EN | OUT | INTP | INTN | MODE[2:0] | |||||
| Access | R/W | R | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bit 7 – EN CLC Enable
| Value | Description |
|---|---|
| 1 | Configurable logic cell is enabled and mixing signals |
| 0 | Configurable logic cell is disabled and has logic zero output |
Bit 5 – OUT Logic cell output data, after LCPOL. Sampled from CLCxOUT.
Bit 4 – INTP Configurable Logic Cell Positive Edge Going Interrupt Enable
| Value | Description |
|---|---|
| 1 | CLCxIF will be set when a rising edge occurs on CLCxOUT |
| 0 | Rising edges on CLCxOUT have no effect on CLCxIF |
Bit 3 – INTN Configurable Logic Cell Negative Edge Going Interrupt Enable
| Value | Description |
|---|---|
| 1 | CLCxIF will be set when a falling edge occurs on CLCxOUT |
| 0 | Falling edges on CLCxOUT have no effect on CLCxIF |
Bits 2:0 – MODE[2:0] Configurable Logic Cell Functional Mode Selection
| Value | Description |
|---|---|
| 111 | Cell is 1-input transparent latch with Set and Reset |
| 110 | Cell is J-K flip-flop with Reset |
| 101 | Cell is 2-input D flip-flop with Reset |
| 100 | Cell is 1-input D flip-flop with Set and Reset |
| 011 | Cell is SR latch |
| 010 | Cell is 4-input AND |
| 001 | Cell is OR-XOR |
| 000 | Cell is AND-OR |