11.13.28 PIR9
Note:
- Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software must ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
Name: | PIR9 |
Address: | 0x4BF |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
DMA3AIF | DMA3ORIF | DMA3DCNTIF | DMA3SCNTIF | CM1IF | |||||
Access | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | ||||
Reset | 0 | 0 | 0 | 0 | 0 |
Bit 7 – DMA3AIF DMA3 Abort Interrupt Flag
Value | Description |
---|---|
1 | Interrupt has occurred (must be cleared by software) |
0 | Interrupt event has not occurred |
Bit 6 – DMA3ORIF DMA3 Overrun Interrupt Flag
Value | Description |
---|---|
1 | Interrupt has occurred (must be cleared by software) |
0 | Interrupt event has not occurred |
Bit 5 – DMA3DCNTIF DMA3 Destination Count Interrupt Flag
Value | Description |
---|---|
1 | Interrupt has occurred (must be cleared by software) |
0 | Interrupt event has not occurred |
Bit 4 – DMA3SCNTIF DMA3 Source Count Interrupt Flag
Value | Description |
---|---|
1 | Interrupt has occurred (must be cleared by software) |
0 | Interrupt event has not occurred |
Bit 0 – CM1IF CMP1 Interrupt Flag
Value | Description |
---|---|
1 | Interrupt has occurred (must be cleared by software) |
0 | Interrupt event has not occurred |