11.13.20 PIR1

Peripheral Interrupt Request Register 1
Note:
  1. Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software must ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
  2. The external interrupt GPIO pin is selected by the INTxPPS register.
  3. I2C2EIF is a read-only bit. To clear the interrupt condition, all bits in the I2C2ERR register must be cleared.
  4. I2C2IF is a read-only bit. To clear the interrupt condition, all bits in the I2C2PIR register must be cleared.
  5. I2C2TXIF and I2C2RXIF are read-only bits. To clear the interrupt condition, the CLRBF bit in I2C2STAT1 must be set.
Name: PIR1
Address: 0x4B7

Bit 76543210 
 I2C2EIFI2C2IFI2C2TXIFI2C2RXIFACTIFADIFADTIFINT0IF 
Access RRRRR/W/HSR/W/HSR/W/HSR/W/HS 
Reset 00000000 

Bit 7 – I2C2EIF  I2C2 Error Interrupt Flag(3)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 6 – I2C2IF  I2C2 Interrupt Flag(4)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 5 – I2C2TXIF  I2C2 Transmit Interrupt Flag(5)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 4 – I2C2RXIF  I2C2 Receive Interrupt Flag(5)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 3 – ACTIF Active Clock Tuning Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred

Bit 2 – ADIF ADC Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred

Bit 1 – ADTIF ADC Threshold Interrupt Flag

ValueDescription
1 Interrupt event has not occurred
0 Interrupt has occurred

Bit 0 – INT0IF  External Interrupt 0 Interrupt Flag(2)

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred
Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software must ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The external interrupt GPIO pin is selected by the INTxPPS register. I2C2EIF is a read-only bit. To clear the interrupt condition, all bits in the I2C2ERR register must be cleared. I2C2IF is a read-only bit. To clear the interrupt condition, all bits in the I2C2PIR register must be cleared. I2C2TXIF and I2C2RXIF are read-only bits. To clear the interrupt condition, the CLRBF bit in I2C2STAT1 must be set.