29.4.1 Synchronous vs. Asynchronous Operation

A new feature of the UTMR module is the isolation of the counter/timer and its control logic to a separate timer clock domain. This can simplify and accelerate the operation of the timer when running on an external clock source. Unfortunately, it also makes the control bits in the Timer Control registers asynchronous to the timer clock domain. It is, therefore, necessary to synchronize the Timer Control Register bits to the timer clock domain by setting the CSYNC bit in the TUxyHLT register. This will cause the synchronization of both the ERS inputs and Control Register bits to the selected counter/timer clock and allow the module to operate completely asynchronous from the system clock.

The synchronization logic produces a delay between the assertion of a signal and its effect in operation. Any signal that goes from the processor domain to the timer domain (like assertion/de-assertion of ON or ERS controls) requires three counter/timer clocks to synchronize. Any signal that goes from the timer domain to the processor domain (like assertion/de-assertion of ON bit, RUN bit, ERS controls, output and interrupt signals) requires three system clocks to synchronize. This delay is acceptable in synchronous applications because the start, reset, and stop events are delayed equally, and there is no net change to the counter sequence.

Figure 29-2 shows clock synchronization with the ON bit (Start) and ERS Reset (Stop), whereas Figure 29-3 shows clock synchronization with setting/clearing of the ON bit (Start/Stop). If an external clock source is selected, then the UTMR will also continue to run during Sleep and can generate interrupts on Start, Stop or Reset, which will wake up the processor.

Figure 29-2. Clock Synchronization with ON Bit and Stop Condition
Figure 29-3. Clock Synchronization with ON Bit and Off Condition
Clearing the CSYNC bit will disable the synchronization logic. When CSYNC = 0, ERS asynchronously gates the clock and/or resets the timer, according to Start, Reset and Stop options. It is possible that the timer clock may transition at the same time that the ON bit is set by the user or an ERS event occurs or a CLR or CAPT command is passed (a clock collision), which may cause unpredictable results to the counter value. Setting CSYNC = 1 removes this uncertainty.
Important: Using an external clock synchronizer, like the CLC or the comparator sync logic, can allow synchronous applications with CSYNC = 0, but clock rate limitations may apply at the device level.

The ON bit must be set for all counting operations. With START = ‘b00 (no ERS Start), setting ON will start the timer as though a Start condition occurred. With START > ‘b00 (ERS edge/level-triggers Start), setting ON prepares the timer for an ERS Start condition and enables the ERS detection logic.

ON will return to ‘0’ when a hardware Stop condition occurs or when written by software, except as noted in the One Shot Mode section. Figure 29-4 and Figure 29-5 below show timing examples for One Shot mode with CSYNC = 1 and CSYNC = 0, respectively.

Figure 29-4. Synchronization and Prescaler Timing (CSYNC = 1)
Figure 29-5. Synchronization and Prescaler Timing (CSYNC = 0)