20.3.4 PORTWDF
Note:
- This register can only be written when the clock to the module is disabled. See Signal Routing Port Clock section for details.
| Name: | PORTWDF |
| Address: | 0x010B |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DF7 | DF6 | DF5 | DF4 | DF3 | DF2 | DF1 | DF0 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 0, 1, 2, 3, 4, 5, 6, 7 – DFn Signal Routing Port Data Flip Flop Enable
| Reset States: |
|
| Value | Description |
|---|---|
| 1 | Signal Routing Port input routed through flip-flop to output |
| 0 | Signal Routing Port input connected directly to output |