20.3.1 PORTW

Signal Routing Port Output

Note:

Writes to PORTW update the ‘PORTW write’ register whereas reads come from ‘PORTW read’ register. See Signal Routing Port Output section for details.
There must be one instruction cycle between write and read of this register, otherwise previous value will be read.
PORTW is not updated when a debug session is active.
This register can only be written when the clock to the module is disabled. See Signal Routing Port Clock section for details.

Name:	PORTW
Address:	0x100


Bit	7	6	5	4	3	2	1	0
	RW7	RW6	RW5	RW4	RW3	RW2	RW1	RW0
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 0, 1, 2, 3, 4, 5, 6, 7 – RWn Output data for software read of Signal Routing port

Reset States:

POR/BOR = 00000000

All Other Resets = 00000000

Writes to PORTW update the ‘PORTW write’ register whereas reads come from ‘PORTW read’ register. See Signal Routing Port Output section for details. There must be one instruction cycle between write and read of this register, otherwise previous value will be read. PORTW is not updated when a debug session is active. This register can only be written when the clock to the module is disabled. See Signal Routing Port Clock section for details.