8.3 Power Management Unit

The Microchip SAM9X75 System-On-Module Series is supplied by an external 5V supply (5V_MAIN) and generates its own internal supplies by interfacing with the Microchip MCP16502 power management unit.

The MCP16502 is a fully-featured Power Management Integrated Circuit (PMIC), cost and size-optimized for Microchip MPU devices such as the SAM9X75 SiP.

The MCP16502 integrates four DC-DC buck regulators used for system supplying and two auxiliary LDOs for customer purpose.

  • All buck channels can support loads up to 1A. All bucks are 100% duty cycle capable.
    • The DCDC1, set to 3.3V, supplies all pads of the embedded devices. This power rail also offers a 600-mA load to customer applications through VDD_3V3 pins.
    • The DCDC2, set to 1.35V, supplies the DDR3L memory and the DCDC2, set to 1.8V, supplies the DDR2 memory. This power rail also offers a 600-mA load to customer applications through VDDIODDR pins.
    • The DCDC3, set to 1.15V, supplies the microprocessor core. It is used internally only.
    • The DCDC4, set to 1.15V, supplies the Gigabit Ethernet digital core. It is used internally only.
  • One 300-mA LDO is provided so that sensitive analog loads can be supported. The LDO output voltage, named VLDO1 (pin 84), is configured by a three-state pin named SEL_VLDO1 (pin 85) at power-up and can deliver 1.8V, 2.5V or 3.3V. Other voltage values can be reached after system initialization by an I²C interface access.
  • One 300-mA LDO is provided so that sensitive analog loads can be supported. The LDO output voltage, named VLDO2 (pin 83), is disabled by default at power-up. Output voltage values are set through an I²C interface access after system initialization.

The default power channel sequencing is built-in as required by the Microchip SAM9X75 MPU device.

Active discharge resistors are provided on each output. All buck channels support safe start-up into pre-biased outputs.

The MCP16502 is available in a 5x5 mm 32-pin VQFN package.

For more information, refer to the MCP16502 PMIC data sheet (see Reference Documents).

The VLDO1 voltage output of the LDO is controlled at boot by configuration of SEL_VLDO1 (pin 85). The default values are selectable among three options corresponding to three different states of the relevant pin: connected to ground (Low), connected to input supply (High) or left unconnected (High-Z). The VLDO1 default voltage can be selected by means of the SEL_VLDO1 pin, as shown in Table 8-4.
Table 8-4. VLDO1 Voltage vs SEL_VLDO1 Pin
SEL_VLDO1 StatusVLDO1 Voltage
Low (grounded)1.8V
High-Z (not connected)2.5V
High (up to 5V_MAIN)3.3V

The LPM pin of the Microchip SAM9X75 System-On-Module Series, combined with the HPM and PWRHLD status pins of the MCP16502 PMIC, defines different power states as illustrated in Table 8-5.

Note: HPM is forced to 0 by hardware, since the high-performance feature of the MCP16502 PMIC is not supported by the SAM9X75 SiP MPU device. For more information, refer to the MCP16502 data sheet (see Reference Documents).
Table 8-5. MCP16502 Default Power States
PWRHLDLPMHPMBuck1Buck2Buck3Buck4LDO1LDO2nRSTPower State(1)
000OffOffOffOffOffOffLowOff
010OffOn(2)OffOn(2)OffOffLowHibernate mode
110On(2)On(2)On(2)On(2)OnOffHiZLow-Power mode
100On(3)On(3)On(3)On(3)OnOffHiZActive mode
Note:
  1. Only allowed modes are listed. If some PWRHLD/LPM/HPM combination is not listed, then such mode is not allowed.
  2. In this mode, the DCDC is configured in Automatic Pulse-Frequency Modulation (Auto-PFM) mode.
  3. In this mode, the DCDC is configured in Force Pulse-Width Modulation (FPWM) mode.

For more information about the use of the MCP16502 LPM feature, refer to the MCP16502 data sheet (see Reference Documents).

The LPM pin can be managed externally, as shown in the figure below.

Figure 8-4. LPM Control Schematic Example