53.6.7 Synchronization

Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read.

The following bits are synchronized when written:

  • Software Reset bit in the Control A register (CTRLA.SWRST)
  • Enable bit in the Control A register (CTRLA.ENABLE)

The following registers need synchronization when written:

  • Control B Clear and Control B Set registers (CTRLBCLR and CTRLBSET)
  • Status register (STATUS)
  • Prescaler and Prescaler Buffer registers (PRESC and PRESCBUF)
  • Compare Value x and Compare Value x Buffer registers (CCx and CCBUFx)
  • Filter Value and Filter Buffer Value registers (FILTER and FILTERBUF)
  • Counter Value register (COUNT)

Required write synchronization is denoted by the "Write-Synchronized" property in the register description.

The following registers are synchronized when read:

  • Counter Value register (COUNT): the synchronization is done on demand through READSYNC software command (CTRLBSET.CMD)

Required read synchronization is denoted by the "Read-Synchronized" property in the register description.