63 Revision History

Table 63-1. Rev L. - 08/2023
Section Name or Type	Change Description
General	No content changes compared with the previous revision.

Table 63-2. Rev K. - 03/2023
Section Name or Type	Change Description
Configuration Summary	Updated Memory columns with new titles and specifications
Block Diagram	Updated the Block Diagram with a new figure
High-Speed Bus System	Updated Configuration with a naming clarification in Table 10-2
DSU	Updated the STATUSB register with new verbiage for the PROT bit
DMAC	Added hyphens to clarify information in the tables for the TRIGACT and TRIGSRC bitfields in the CHCTRLA Register
NVMCTRL	Updated the verbiage in Memory Organization Restructured the line items and added new information to Security Bit Set Procedure Updated bit naming in Chip Erase Updated commands in the table for the CMD bitfield in the CTRLB Register Reorganized the table for the PSZ bitfield in the PARAM register Updated the bitfield reset properties for the PSZ and SBLK bitfields in the SEESTAT register
SERCOM USART	Clarified verbiage for the Tx buffer in Data Transmission Added a new note to LIN Host Added a note to the HDRDLY and BRKLEN bitfields in the CTRLC register
USB	Updated the FNUM register, and removed bits 2-0 MFNUM. Updated the CTRLB register and removed these bits: 8,7,6,5 Updated the INTENCLR register and removed Bit 1 MSOF Updated the INTENSET register and removed Bit 1 MSOF Updated the INTFLAG register and removed Bit 1 MSOF Updated the EPCFGn register and removed bit 7 NYETDIS Updated the CTRLB register and removed bits TSTK and TSTJ Updated the HSOFC register and removed one table under the FLENCE bit Updated the STATUS register bit SPEED Updated the FNUM register, removed the Bit 2-0 MFNUM Updated the FLENHIGH register bit 7:0 FLENHIGH Updated the BINTERVALn register Bits 7:0 – BINTERVAL
CAN	Updated the NBTP register with new verbiage
ADC	Added a new section Rail-to-Rail Operation
TC	Added line item 4 to Capture Operations
PDEC	Clarified signal names in the Block Diagram
Electrical Characteristics at 85°C	Added a row for Tstart to Table 54-44 in Crystal Oscillator (XOSC) Characteristics
Electrical Characteristics at 105°C	Added a new table to Crystal Oscillator (XOSC) Characteristics
Electrical Characteristics at 125°C	Added a new table to Crystal Oscillator (XOSC) Characteristics
Schematic Checklist	Added and clarified verbiage in the Introduction Added a new Important note to Operation in Noisy Environment Added a new note and removed obsolete content from External Reset Circuit Added a new note and clarified verbiage in Programming and Debug Ports Removed obsolete information from USB Interface

Rev J. - 08/2022

Terminology used in this document may not match with the contents of the current revision of the device errata or other Microchip documentation and collateral. If there are any questions or concerns regarding terminology, contact a Microchip Support or Sales Representative.

The following updates were performed in this revision:

Table 63-3. Rev J. - 08/2022
Section Name or Type	Change Description
GENERAL	The I²C, SPI and I²S standards use the terminology "Master" and "Slave". The equivalent Microchip terminology used in this document is "Host" and "Client" respectively.
GCLK	Added a new step to Selecting the Clock Source for a Peripheral
RTC	Updated the following registers with new register properties: COUNT in COUNT32 Mode COUNT in COUNT16 Mode
OSCCTRL	Updated Additional Features with new notes and text for changing the reference clock source
EVSYS	Updated the naming of the CHANNELn Register
SERCOM USART	Updated Start-of-Frame Detection with new content for the first paragraph
SERCOM SPI	Added new text to I/O Lines
AC	Added third note to Window Operation Added a note to the ENABLE bit in the CTRLA Register Updated the naming for the COMPCTRLn Register
TC	Removed an erroneous reference to the DMAOS bitfield in the CTRLA Register for 8-bit Mode, 16-bit Mode, and 32-bit Mode Replaced the bitfield description for the CMD bitfield in the CTRLBCLR Register for 8-bit Mode, 16-bit Mode, and 32-bit Mode Added an Important note to the CMD bitfield in the CTRLBSET Register for 8-bit Mode, 16-bit Mode, and 32-bit Mode Updated the Register Property for the following Registers: COUNT 8-bit Mode CCx 8-bit Mode COUNT 16-bit Mode COUNT 32-bit Mode
TCC	Added a new note to Counter Operation Added a note to the SWRST Bitfield in the CTRLA Register The Bitfield description for the CMD bitfield was rewritten in the CTRLBCLR Register Added notes to the CMD and DIR Bitfields in the CTRLBSET Register Updated the Register properties for the following Registers: STATUS WAVE CCx PATTBUF PERBUF CCBUF COUNT
PTC	The Functional Description was reworked to include references to Microchip Touch
I²S	Added a note to Principle of Operation Added a note to the FSWIDTH bitfield of the CLKCTRLn Register
USB	Restructured all Register sets and corrected register offsets
PDEC	Updated the signal equation in Input Selection and Filtering
Electrical Characteristics at 85°C	Updated the Analog Comparator Characteristics table with new Conditions values for Vhys, min, and max values Updated Table 54-13. I/O Pins Maximum Output Current with new values
Electrical Characteristics at 105°C	Updated the Analog Comparator Characteristics table with new min and max values
Electrical Characteristics at 125°C	Updated the Analog Comparator Characteristics table with new min and max values

Table 63-4. Rev H. - 02/2022
Section Name or Type	Change Description
Analog Comparators - AC	Updated the Features with a new DAC0 input Updated the Block Diagram to display DAC0 instead of DAC Removed erroneous 0x3 information from the COMPCTRLx.SPEED entry in Comparator Configuration Updated the following registers: STATUSA with new info for the WSTATE0 bitfield COMPCTRLn with new information for the HYST Bitfield
Electrical Characteristics at 85°C	Updated the Analog Comparator Characteristics table in Analog Comparator (AC) Characteristics. Added a new note to the table.
Electrical Characteristics at 105°C	Updated the Analog Comparator Characteristics table in Analog Comparator (AC) Characteristics. Added a new note to the table.
Electrical Characteristics at 125°C	Updated the Analog Comparator Characteristics table in Analog Comparator (AC) Characteristics. Added a new note to the table.

Table 63-5. Rev G. - 01/2021
Section Name or Type	Change Description
General	Along with the updates listed below, numerous typographical and minor editorial updates were made to this document.
Features	Updated Memories to show proper nomenclature for SmartEEPROM.
Configuration Summary	Updated Table 1-2 with new I²S specs for SAME51G18 and SAME51G19.
I/O Multiplexing and Considerations	Updated Table 6-34 GPIO Clusters, removed erroneous GPIO designations for the 100 pin package.
Memories	Updated Table 9-4 for bit position 75:64.
CMCC	Removed erroneous bitfields from the TYPE Register.
DSU	Updated SmartEEPROM nomenclature in Chip Erase Updated references to SmartEEPROM in Table 12-3 of 32-bit Cyclic Redundancy Check CRC32 Updates table 12-6 in System Services Availability when Accessed Externally and Device is Protected with proper verbiage for SmartEEPROM Updated ENTRY0 and ENTRY1 registers with correct numbering
Clock System	Updated the Clock Request Routing Diagram in On Demand Clock Requests.
GCLK	Updated the GENCTRLn register with a new bitfield length for the SRC bit, and added new data to the end of table 14-4 Generator Clock Source Selection.
MCLK	Updated the table in Peripheral Clock Masking with new values for the ADC, NVMCTRL, and removed a reference to the PTC Updated the bitfield numbering and reset values in the following registers: AHBMASK APBCMASK
PM	Updated figure 18-2 in Sleepwalking Updated the register offset for the PWSAKDLY Register
SUPC	Removed an erroneous BOD12 reference from Enabling, Disabling, and Resetting.
RTC	Updated the COUNT32 Register with a new note.
DMAC	Updated the following registers with new bitfield verbiage: BASEADDR WRBADDR SRCADDR DSTADDR
GMAC	Updated the following registers with new bitfield information for bit 27: ISR IER IDR IMR Updated the TPB1ADR bit in the TPSF Register Updated the RPB1ADR bit in the RPSF Register Added the TPFCP Register Renamed the bitfield in the TLPITI Register from RLPITI to TLPITI
NVMCTRL	Updated verbiage for SmartEEPROM throughout the entire chapter Corrected typographical errors in Safe Flash Update Using Dual Banks Updated the CELCK Description in the table for the CMD bit in the CTRLB Register
ICM	Updated the Functional Description Overview topic with new verbiage for the end of list marker and WRAP bit setting.
OSCCTRL	Updated references for the SWBCK bit to the SWBEN bit in the Clock Switch section of Clock Failure Detection Operation.
OSC32KCTRL	Added a new note to 32 kHz Ultra Low-Power Internal Oscillator (OSCULP32K) Operation, and removed erroneous text references to the CALIB bit Updated the OSCULP32K Register with the removal of the erroneous CALIB bit, and converted it to a Reserved bit
EVSYS	Updated the following registers with new bitfield numbering: CHANNEL USERm
PORT	Updated the bitfield numbering for the PORTEIx, EVACTx, and PIDx bits in the EVCTRL Register.
SERCOM I²C	Corrected references for the LOWTOUTEN bit in Initialization Updated the CTRLA (Slave) Register with corrections to the name for the LOWTOUTEN bit Added a new LENERR bit to the STATUS (Slave) Register Updated the CTRLA (Master) Register with corrections to the name for the LOWTOUTEN bit
QSPI	Updated Serial Clock Phase and Polarity with new values for the Capture SCK Edge column in table 37-2 Added a new note to QSPI Serial Memory Mode Updated the bitfield Access for the ENABLE bit in the CTRLA Register
USB	The STATUS (Device Registers - Common) was updated with new bit field data.
CAN	Updates were made to the following Registers for bitfield naming, numbering, and typographical corrections: MRCFG ILE NDAT1 NDAT2 TXBRP TXBAR TXBCR TXBTO TXBCF TXBTIE TXBCIE TXEFS
SDHC	Removed erroneous Asynchronicity text in Clocks Updated the MAXBLKL bitfield with proper numbering in the CA0R Register Updated the PVR Register with the addition of the DRVSEL bitfield
CCL	Updated the Block Diagram to properly display only one layer Updated Signal Description with new Pin names Updated the LUTCTRL Register name
ADC	Removed erroneous RBSSW bitfield from the SYNCBUSY Register.
TC	Updated the Note in Capture Operations.
TCC	Updated the Block Diagram to display six Compare/Capture units Updated Principle of Operation to state six compare/Capture channels instead of four. Updated the following Registers: CTRLA with a new bit numbering for the CPTENx bitfield EVCTRL with a new bit numbering for the MCEOx and MCEIx bitfields The following registers have updates made to the MCx bitfields: INTENCLR INTENSET INTFLAG STATUS with a new bitfield numbering for CMPx and CCBUFVx
PCC	Removed erroneous text for transfer status signals from Principle of Operation Updated the text for line item number five in With DMAC Updated the following Registers with the removal of erroneous bitfields: IER IDR IMR ISR
PDEC	Added a new section to the chapter titled Secure Decoder Detection.
Electrical Characteristics at 85°C	Added a new note to I/O Pin Characteristics Removed erroneous BIASREFBUF references from the Power Consumption table in Analog-to-Digital Converter (ADC) Characteristics Removed the BANDGAP reference from Table 54-34 in Voltage References In Internal Ultra Low Power 32 kHz RC Oscillator (OSCULP32K) Characteristics an erroneous Calibration column was removed from table 54-49
Appendix A	Added a new Appendix section for ISELED Specifications.

Table 63-6. Rev. F - 05/2020
Section Name or Type	Change Description
Features	Updated the number of Temperature sensors Corrected Wake-up pins from 4 to 5
I/O Multiplexing and Considerations	Added a new note to Table 6-34 GPIO Clusters.
Power Supply and Startup Considerations	Updated VDDIO and VDDANA information in Power Supplies Updated the Power Domain Block Diagram to properly display the POR Updated Section 7.3.3 I/O Pins with a more detailed explanation of the pins
GCLK	Corrected the number of Peripheral Channels from 64 to 48 in Principle of Operation Removed CTRLA register from section 15.8 Register Description
MCLK	Added a new note to the AHBMASK register, and modified the access attribute of bits 11,7 and 5 from "R" to "R/W.”
DMAC	Added disable information to the SWRST bit in the CTRL register Updated the PRICTRL0 Register with new bit information for the QOS bit
RTC	Corrected the Tamper channels from 4 to 5 in Tamper Detection Added a new note to Timestamp
EVSYS	Updated the Register offset equations for the following registers: CHINTENCLR CHINTENSET CHINTFLAG CHSTATUSn
SERCOM USART	Corrected the Baud Rate Divider in the Clock Generation figure for Clock Generation and Selection.
I²S	Updated Figure 51-8 and 51-9 in I²S Application Examples.
USB	Updated the EPSTATUSn register with new table information for the BK1RDY bit Removed an incorrect reference to INTFLAGA in Figure 38.9 Device Interrupt Removed the MFNUM bit from the ENUM register
CAN	Updated Timestamp Generation with a revised bit name for CCCR.BRSE and a note about bit rate switching Corrected the TSC value from 15 to 16 in Timeout Counter
TRNG	Updated reset information for the DATA register.
TC	Corrected GCLK_TC to GCLK_TCx and CLK_TC_CNT to CLK_TCx_CNT throughout the chapter.
TCC	Corrected GCLK_TCC to GCLK_TCCx throughout the chapter Corrected the Register representation for: Pattern Pattern Buffer
ADC	Updated the REFSEL bit table in the REFCTRL register.
AES	The name of the register changed from DATA to INDATA
DAC	Updated the CTRLB register with new information for the REFSEL bit.
Electrical Characteristics at 85°C	Updated the note for the Absolute Maximum Ratings table Updated the table for General Operating Ratings Updated the note in Injection Current Updated Supply Characteristics with a new table Updated the tables in I/O Pin Characteristics with correct conditions and notes Replaced the tables and associated notes with new information in Brown-Out Detectors (BOD) Characteristics Replaced the tables with new information in Analog-to-Digital Converter (ADC) Characteristics Updated the tables in Analog Comparator (AC) Characteristics with correct parameter name Updated the tables NVM Characteristics with correct format, parameter name, and new notes Updated Crystal Oscillator (XOSC) Characteristics with a simplified schematic for Oscillator Connection Updated External 32 kHz Crystal Oscillator (XOSC32K) Characteristics with a simplified schematic for Oscillator Crystal Connection and corrected the Load Capacitance equation Removed 25℃ data from Ultra-Low-Power Internal 32 kHz RC Oscillator Electrical Characteristics in Internal Ultra Low Power 32 kHz RC Oscillator (OSCULP32K) Characteristics Merged the current values in the DFLL48M Power Consumption table in Digital Frequency Locked Loop (DFLL48M) Characteristics Reorganized SERCOM in SPI Mode Timing to show the figures before the table Added t_MOH parameter value in Table 54-56. SPI Timing Characteristics and Requirements Added max value for parameter t_SCKR and t_SCKf in Table 54-56. SPI Timing Characteristics and Requirements Added new note to QSPI Maximum Frequency Examples in QSPI Characteristics Reorganized GMAC Characteristics to display the diagrams before the tables Reorganized I²S Characteristics to display the images before the tables Updated Table 54-63. I2S Timing Characteristics and Requirements for parameter f_{M_SCKO} Added new figures and tables to PCC Characteristics Added the following new sections: TC Characteristics TCC Characteristics PDEC Characteristics
Electrical Characteristics at 105°C	Added a new note to General Operating Ratings Added new tables to Brown-Out Detectors (BOD) Characteristics 105°C Added new tables and notes to Analog-to-Digital Converter (ADC) Characteristics (105°C) Removed the Multiple Crystal Oscillator Electrical Characteristics Table from Crystal Oscillator (XOSC) Characteristics (105°C) Updated NVM Characteristics with correct format, parameter name, and a new note
Electrical Characteristics at 125°C	Updated the table in General Operating Ratings with a new note Updated Injection Current with new notes Updated Brown-Out Detectors (BOD) Characteristics (125°C) with new tables and notes Removed the Power Supply Current Requirement table Updated Analog-to-Digital Converter (ADC) Characteristics (125°C) with new tables and new notes Added a new note to the Analog Comparator Characteristics table for the operating voltage range. Updated NVM Characteristics (125C) with correct format, parameter name, and a new note Removed Multiple Crystal Oscillator Electrical Characteristics Table from Crystal Oscillator (XOSC) Characteristics (125°C) Removed 32 kHz Crystal Oscillator Electrical Characteristics table from External 32 kHz Crystal Oscillator (XOSC32K) Characteristics (125°C)
Package Information	Updated Junction Temperature with a new table Added 59.3.9 120-ball TFBGA (AEC-Q100 Grade 1)
Schematic Checklist	Updated the Schematics in Power Supply Connections with a 100nF connection

Table 63-7. Revision E - 06/2019
Section Name or Type	Change Description
Introduction	Updated sections: Updated Features Updated the Configuration Summary
Processor and Architecture	Updated Interrupt Line Mapping
CMCC	Updated sections: Data Cache Disable Instruction Cache Disable
GCLK	Updated the PCHCTRLm register
PM	Updated Backup Mode
RTC	Count32 Registers updated: CTRLA EVCTRL INTENCLR INTENSET INTFLAG SYNCBUSY GPn Count16 Registers updated: CTRLA EVCTRL INTENCLR INTENSET INTFLAG SYNCBUSY GPn The following Clock registers were updated: CTRLA EVCTRL INTENCLR INTENSET INTFLAG SYNCBUSY GPn
DMAC	The following topics were updated: Initialization Enabling, Disabling and Resetting Transfer Descriptors The following registers were updated: CTRL SWTRIGCTRL INTSTATUS BUSYCH
GMAC	The following topics were updated: Features Pause Frame Reception
OSCCTRL	The following topics were updated: Digital Phase Locked Loop (DPLL) Operation
SERCOM-SPI	Updated the following topics: Clock Generation
QSPI	Updated the following topics: Continuous Read Mode
SDMMC	Updated the following registers: PSR PCR NISTR NISTER HC2R EMMC HC2R SDIO CA0R CA1R MCCAR ASAR PVRx MC1R ACR
ADC	Updated the INPUTCTRL register
AC	Updated the following sections: Signal Description
TC	Updated the following sections: Counter Mode
TCC	Updated the following sections: Capture Operations Updated the following registers: WAVE
I²S	Updated the following sections: DMA Operation Updated the following registers: CTRLA INTENCLR INTENSET INTFLAG SYNCBUSY TXCTRL RXCTRL
Electrical Characteristics at 85°C	Updated the following sections: General Operating Ratings Injection Current Power Consumption Analog-to-Digital Characteristics Digital-to-Analog Converter Characteristics Added in new section: PTC Characteristics
Electrical Characteristics at 105°C	Updated the following sections: Power Consumption Digital-to-Analog Converter Characteristics Analog-to-Digital Characteristics Added new section: PTC Characteristics
Electrical Characteristics at 125°C	Updated the following sections: Power Consumption Analog-To-Digital Characteristics Digital-to-Analog Characteristics Added new section: PTC Characteristics

Table 63-8. Rev. D - 12/2018
Section Name or Type	Change Description
Ordering Information	Added AEC-Q100 Qualified package type.
I/O Multiplexing and Considerations	Added information for GRXDV pin for 64-pin package devices.
AEC Q-100 Grade 1, 125°C Electrical Characteristics	Introduced device part numbers with AEC Q-100 Grade 1.

Table 63-9. Rev. C - 11/2018
Section Name or Type	Change Description
Ordering Information	Added ordering information for 105°C and 125°C temperature grade.
Pinout	Exposed pad info added for VQFN package.
I/O Multiplexing and Considerations	Corrected typographical errors for pin numbers PB19 and PB23.
Memories	Clarified NVM User Row size in table 9-1.
Processor and Architecture	Corrected typographical errors in section 10.2.2 Interrupt Line Mapping for SERCOMx interrupt line 7.
MCLK	Corrected typographical errors related to R/W bits for 15.8.8 APBA Mask Register.
PM	Updated Figure 18-2 Operating Conditions and SleepWalking to reflect that PL0 is not applicable to this product.
SUPC	Updated INTENCLR, INTENSET, INTFLAG, and STATUS Registers to reflect factory preprogramming of BOD12.
DMAC	Removed CHIP.ID information as it is not applicable to this product.
EVSYS	Corrected typographical errors in the USERm Register offset.
CCL	Internal Events Inputs Selection (EVENT) section was updated by removing ASYNCEVENT related information. Alternate 2 TC input source not applicable and was removed for LUTCTRL.INSELx bits.
ADC	Added clarification for INTREF to 45.8.6 Reference Control(REFCTRL).
TC	48.7.1 Register Summary - 8-bit Mode Updated register bitfield with indexing to display usage. 48.7.2 Register Summary - 16-bit Mode Updated register bitfield with indexing to display usage. Removed inapplicable register PER & PERBUF register information. 48.7.3 Register Summary - 32-bit Mode Updated register bitfield with indexing to display usage. Removed inapplicable register PER & PERBUF register information.
TCC - Timer/Counter for Control Applications	Table 49-4. Output Matrix Channel Pin Routing Configuration updated to show all supported 6 capture channels. Table 49-8. Fault and Capture Action updated by adding missing CAPTMARK value for CAPTURE bit fields. Register INTENCLR, INTENSET, INTFLAG updated with missing UFS bit. Removed unsupported bit info for the register 49.8.15 Pattern (PATT). Missing POLx bits added to the register 49.8.16 Waveform (WAVE). 49.7 Register Summary Updated register bitfield with indexing to display usage.
54 Electrical Characteristics at 85°C	Clarified how C_LEXT can be computed in section 54.12.1 Crystal Oscillator (XOSC) Characteristics and 54.12.2 External 32 kHz Crystal Oscillator (XOSC32K) Characteristics Clarified capacitor requirements in Table 54-18. External Components Requirements in Switching Mode and Table 54-19 Decoupling Requirements. Condition shown for VREF parameter is removed in table 54-24. Operating Conditions. Conditions specified for table 54-29 Differential Mode is clarified for INL & DNL with Internal voltage reference. Table 54-35. Flash Timing Characteristics is updated for Chip Erase maximum time. Added the missing note in Table 54-44. Ultra-Low-Power Internal 32kHz Oscillator Electrical Characteristics. Added the missing note in Table 54-48. Fractional Digital Phase Lock Loop Characteristics Typo for the maximum value of tMOH in the Table 54-51. SPI Timing Characteristics and Requirements addressed. Table 54-53. QSPI Maximum Frequency examples updated.
Electrical Characteristics at 105°C	Introduced device part numbers with Electrical Characteristics for 105°C temperature grade.
Electrical Characteristics at 125°C	Introduced device part numbers with Electrical Characteristics for 125°C temperature grade.

Table 63-10. Rev. B - 4/2018
Section Name or Type	Change Description
Features	Updated CAN FD reference. Added 120-ball TFBGA package.
Configuration Summary	Added 120-ball TFBGA to the family feature tables.
Ordering Information	Updated the notes for devices in WLCSP packages. Updated Package Type, adding CT = TFBGA.
Pinout	Added the 120-ball TFBGA package pinout diagram.
Multiplexed Signals	Added 120-ball TFBGA and updated Note 3 (see Table 6-1.
OSC32KCTRL - 32 kHz Oscillators Controller	Added the EN1K and EN32K bits to the OSCULP32K register (see OSCULP32K29.8.9 32KHz Ultra Low Power Internal Oscillator (OSCULP32K) Control).
SERCOM - Serial Communication Interface	Added Fractional Baud information to the Baud Rate Equations (see Table 33-2).
QSPI - Quad Serial Peripheral Interface	Added equations to the BAUD register (see BAUD37.8.3 Baud Rate).
CAN - Control Area Network	Updated the Overview. Updated ISO 11898 references throughout the chapter.
Public Key Cryptography Controller (PUKCC)	Added the Public Key Cryptography Library (PUKCL) Application Programmer Interface (API) section.
TCC - Timer/Counter for Control Applications	Updated the number of TCC instances to 5 (4:0).
54 Electrical Characteristics at 85°C	(1) Improved SPI maximum speed information in Table 54-56. (2). Added example for QSPI maximum frequency examples Table 54-58.
Packaging Information	Added the 120-ball TFBGA package (see 59.3.8 120-ball TFBGA).

Rev. A - 07/2017

This is the initial release of the document.