48.7.2.1 Control A
| Name: | CTRLA |
| Offset: | 0x00 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection, Write-Synchronized, Enable-Protected |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| CAPTMODE1[1:0] | CAPTMODE0[1:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| COPEN1 | COPEN0 | CAPTEN1 | CAPTEN0 | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ALOCK | PRESCALER[2:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ONDEMAND | RUNSTDBY | PRESCSYNC[1:0] | MODE[1:0] | ENABLE | SWRST | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 28:27 – CAPTMODE1[1:0] Capture mode Channel 1
| Value | Name | Description |
|---|---|---|
| 0x0 | DEFAULT | Default capture |
| 0x1 | CAPTMIN | Minimum capture |
| 0x2 | CAPTMAX | Maximum capture |
| 0x3 | - | Reserved |
Bits 25:24 – CAPTMODE0[1:0] Capture mode Channel 0
| Value | Name | Description |
|---|---|---|
| 0x0 | DEFAULT | Default capture |
| 0x1 | CAPTMIN | Minimum capture |
| 0x2 | CAPTMAX | Maximum capture |
| 0x3 | - | Reserved |
Bits 20, 21 – COPENx Capture On Pin x Enable
Bit x of COPEN[1:0] selects the trigger source for capture operation, either events or I/O pin input.
| Value | Description |
|---|---|
| 0 | Event from Event System is selected as trigger source for capture operation on channel x. |
| 1 | I/O pin is selected as trigger source for capture operation on channel x. |
Bits 16, 17 – CAPTENx Capture Channel x Enable
Bit x of CAPTEN[1:0] selects whether channel x is a capture or a compare channel.
These bits are not synchronized.
| Value | Description |
|---|---|
| 0 | CAPTEN disables capture on channel x. |
| 1 | CAPTEN enables capture on channel x. |
Bit 11 – ALOCK Auto Lock
When this bit is set, Lock bit update (LUPD) is set to '1' on each overflow/underflow or re-trigger event.
This bit is not synchronized.
| Value | Description |
|---|---|
| 0 | The LUPD bit is not affected on overflow/underflow, and re-trigger event. |
| 1 | The LUPD bit is set on each overflow/underflow or re-trigger event. |
Bits 10:8 – PRESCALER[2:0] Prescaler
These bits select the counter prescaler factor.
These bits are not synchronized.
| Value | Name | Description |
|---|---|---|
| 0x0 | DIV1 | Prescaler: GCLK_TCx |
| 0x1 | DIV2 | Prescaler: GCLK_TCx/2 |
| 0x2 | DIV4 | Prescaler: GCLK_TCx/4 |
| 0x3 | DIV8 | Prescaler: GCLK_TCx/8 |
| 0x4 | DIV16 | Prescaler: GCLK_TCx/16 |
| 0x5 | DIV64 | Prescaler: GCLK_TCx/64 |
| 0x6 | DIV256 | Prescaler: GCLK_TCx/256 |
| 0x7 | DIV1024 | Prescaler: GCLK_TCx/1024 |
Bit 7 – ONDEMAND Clock On Demand
This bit selects the clock requirements when the TC is stopped.
In standby mode, if the Run in Standby bit (CTRLA.RUNSTDBY) is '0', ONDEMAND is forced to '0'.
This bit is not synchronized.
| Value | Description |
|---|---|
| 0 | The On Demand is disabled. If On Demand is disabled, the TC will continue to request the clock when its operation is stopped (STATUS.STOP=1). |
| 1 | The On Demand is enabled. When On Demand is enabled, the stopped TC will not request the clock. The clock is requested when a software re-trigger command is applied or when an event with start/re-trigger action is detected. |
Bit 6 – RUNSTDBY Run in Standby
This bit is used to keep the TC running in standby mode.
This bit is not synchronized.
| Value | Description |
|---|---|
| 0 | The TC is halted in standby. |
| 1 | The TC continues to run in standby. |
Bits 5:4 – PRESCSYNC[1:0] Prescaler and Counter Synchronization
These bits select whether the counter should wrap around on the next GCLK_TCx clock or the next prescaled GCLK_TCx clock. It also makes it possible to reset the prescaler.
These bits are not synchronized.
| Value | Name | Description |
|---|---|---|
| 0x0 | GCLK | Reload or reset the counter on next generic clock |
| 0x1 | PRESC | Reload or reset the counter on next prescaler clock |
| 0x2 | RESYNC | Reload or reset the counter on next generic clock. Reset the prescaler counter |
| 0x3 | - | Reserved |
Bits 3:2 – MODE[1:0] Timer Counter Mode
These bits select the counter mode.
These bits are not synchronized.
| Value | Name | Description |
|---|---|---|
| 0x0 | COUNT16 | Counter in 16-bit mode |
| 0x1 | COUNT8 | Counter in 8-bit mode |
| 0x2 | COUNT32 | Counter in 32-bit mode |
| 0x3 | - | Reserved |
Bit 1 – ENABLE Enable
Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRLA.ENABLE will read back immediately, and the ENABLE Synchronization Busy bit in the SYNCBUSY register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete.
This bit is not enable protected.
| Value | Description |
|---|---|
| 0 | The peripheral is disabled. |
| 1 | The peripheral is enabled. |
Bit 0 – SWRST Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets all registers in the TC, except DBGCTRL, to their initial state, and the TC will be disabled.
Writing a '1' to CTRLA.SWRST will always take precedence; all other writes in the same write-operation will be discarded.