42.8.3 Interrupt Enable Clear
| Name: | INTENCLR |
| Offset: | 0x05 |
| Reset: | 0x00 |
| Property: | PAC Write-Protection |
This register allows the user to disable
an interrupt without doing a read-modify-write operation. Changes in this register will
also be reflected in the Interrupt Enable Set (INTENSET)
register.
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| GFMCMP | ENCCMP | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
Bit 1 – GFMCMP GF Multiplication Complete Interrupt Enable
Writing a '1' to this bit will clear the GF Multiplication Complete Interrupt Enable bit, which disables the GF Multiplication Complete interrupt.
| Value | Description |
|---|---|
| 0 | The GF Multiplication Complete interrupt is disabled. |
| 1 | The GF Multiplication Complete interrupt is enabled. |
Bit 0 – ENCCMP Encryption Complete Interrupt Enable
Writing a '1' to this bit will clear the Encryption Complete Interrupt Enable bit, which disables the Encryption Complete interrupt.
| Value | Description |
|---|---|
| 0 | The Encryption Complete interrupt is disabled. |
| 1 | The Encryption Complete interrupt is enabled. |