55.4 NVM Characteristics

Table 55-19. NVM Flash Read Wait States for Worst Case Conditions
Wait States (WS)	0 WS	1 WS	2 WS	3 WS	4 WS	5 WS	6 WS	Auto WS
Read Operations	1 cycle	2 cycles	3 cycles	4 cycles	5 cycles	6 cycles	7 cycles	n cycles
CPU FMax (MHz)⁽¹⁾	19	38	57	76	95	100	120	120

Note:

VDD > 1.71.

Maximum operating frequencies are given in the table above, but are limited by the Embedded Flash access time when the processor is fetching code out of it. Theses tables provide the device maximum operating frequency defined by the field RWS of the NVMCTRL CTRLA register when automatic wait states (AUTOWS) is disabled. This field defines the number of Wait states required to access the Embedded Flash Memory.