18.5.6 Debug Operation

When the CPU is halted in debug mode, the PM continues normal operation. If standby sleep mode is requested by the system while in debug mode, the power domains are not turned off. As a consequence, power measurements while in debug mode are not relevant.

If Hibernate or Backup sleep mode is requested by the system while in debug mode, the core domains are kept on, and the debug modules are kept running to allow the debugger to access internal registers. When exiting the hibernate or backup mode upon a reset condition, the core domains are reset except the debug logic, allowing users to keep using their current debug session.

If OFF sleep mode is requested while in debug mode, the core domains are reset.

Hot plugging in standby mode is supported.

Hot plugging in Hibernate or backup mode or OFF mode is not supported as the DSU module is not powered.

Cold plugging in Hibernate or backup or OFF mode is supported if the external reset duration is superior to the corresponding sleep mode wakeup time (See Electrical characteristic chapter).

Backup wakeup time is less than 200us in typical case. This value can be higher if voltage scaling in SUPC is enabled. Refers to SUPC for details.