12.13.9 Configuration

Name:	CFG
Offset:	0x1C
Reset:	0x00000002
Property:	PAC Write-Protection


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
				ETBRAMEN	DCCDMALEVEL[1:0]		LQOS[1:0]
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	0	1	0

Bit 4 – ETBRAMEN Trace Control

ETB Ram Enable Writing a one to this bit will reserve the first 32KB of the RAM for the Trace ETB ram buffer. Refer to Memories / SRAM Memory Configuration section for details.

Bits 3:2 – DCCDMALEVEL[1:0] DMA Trigger Level

Value	Description
0x0	DMA Trigger rises when DCC is empty.
0x1	DMA Trigger rises when DCC is full.
0x2 - 0x3	Reserved

Bits 1:0 – LQOS[1:0] Latency Quality Of Service

These bits define the priority access during the memory access. Refer to SRAM Quality of Service.