2.10.2 Timer1 Register (TMR1)

In Asynchronous External Counter mode, (TCS bit (T1CON[1] = 1), TSYNC bit (T1CON[2] = 0) and TECS[1:0] (T1CON[9:8] = ‘0b01)), the Timer1 register (TMR1) remains at the initial set value for five external clock pulses after wake-up from Sleep mode.