2.2.1 Step 1: Entering Flash Programming Mode

For memory programming, the minimum set of hardware connections required to interface an external host to the BM70/71 is illustrated in the following figure. These hardware connections between the host and BM70/71 will allow the host to control the behavior (in other words, to enter the memory programming mode, test mode, communicate and calibrate) of the BM70/71.

Figure 2-2. Required Hardware Interface for Memory Programming

The BM70/71 operation, or mode, is determined by the level of a hardware pin, P2_0. This pin is sampled when the RST_N pin goes active. The RST_N signal must be active for the minimum time, to make sure the pin P2_0 logic level is latched into the IC correctly. Once the BM70/711 enters the applicable mode, communication over the UART interface becomes active. The data or protocol that is used to communicate between the host and BM70/71 is based on the mode the BM70/71 enters after a reset.

To summarize: The memory programming mode is entered when pin P2_0 is latched by the BM70/71 at a logic level ‘0’.

The application, or run mode, where general Bluetooth low energy operation is available, is entered when pin P2_0 is latched by the BM70/71 at a logic level ‘1’. The following table summarizes the use of the P2_0 pin.

Table 2-1. Summary of Modes available based on Pin P2_0

Pin P2_0 Logic Level

Mode

Protocols Enabled

0 – Low
  • Memory programming
  • RF Calibration/RF testing
  • HCI commands
  • HCI-ISDAP commands

1 – High

Application or Run

BM70 command set

The following figures illustrate the timing diagram for the P2_0 pin with respect to the Reset pin and the Input Voltage pin, respectively.

Figure 2-3. Timing Diagram for Pin P2_0 with Respect to Reset Pin
Figure 2-4. Timing Diagram for Pin P2_0 with Respect to Input Voltage