Interconnected fabric containing 32 Basic Logic Elements (BLE)
Each BLE contains
one 4-input LUT and one flip-flop
Schematically
programmable using MPLAB® Code
Configurator
CLB auto-load on
boot
CLB hardware debugging pins
Four external digital
inputs/eight digital outputs via Peripheral Pin Select (PPS)
External clock input
Two Capture/Compare/PWM (CCP)
Modules:
16-bit resolution for
Capture/Compare modes
10-bit resolution for PWM
mode
Two 16-Bit Pulse-Width Modulators
(PWM):
Dual outputs for each PWM
module
Integrated 16-bit
timer/counter
Double-buffered user
registers for duty cycles
Right/Left/Center/Variable Aligned modes of operation
Multiple clock and Reset
signal selections
Four Configurable Logic Cells (CLC):
Integrated combinational and sequential logic
One Configurable 8/16-Bit Timer
(TMR0)
Two 16-Bit Timers (TMR1/3) with
Gate Control
Two 8-Bit Timers (TMR2/4) with
Hardware Limit Timer (HLT)
Programmable CRC with Memory Scan:
Reliable data/program
memory monitoring for fail-safe operation (e.g., Class B)
Calculate 32-bit CRC over any portion of Program Flash Memory
Two Enhanced Universal
Synchronous Asynchronous Receiver Transmitters (EUSART):
RS-232, RS-485, LIN
compatible
Auto-wake-up on
Start
Up to two Host Synchronous Serial
Ports (MSSP):
Serial Peripheral
Interface (SPI) mode
Chip Select
Synchronization
Inter-Integrated Circuit
(I2C) mode
7/10-bit
Addressing modes
SMBus
support
Peripheral Pin Select (PPS):
Enables pin mapping of
digital I/O
Device I/O Port Features:
Up to 35 I/O pins
Individual I/O direction,
open-drain, input threshold, slew rate and weak pull-up control
Interrupt-on-Change (IOC)
on all pins
One external interrupt
pin
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.