Pin Allocation Tables

Table . 8-Pin Allocation Table
I/O

8-Pin

SOIC

DFN

ADCDACComparatorTimersCCP

16-Bit

PWM

CLBCLC

I2C/

SPI

EUSARTIOCInterruptBasic
RA07ANA0DAC1OUT1C1IN0+

T3CKI(1)

T3G(1)

T4IN(1)

PWMIN0(1)

PWMIN1(1)

PWM2ERS(1)

CLBIN3(1)CLCIN3(1)

CK1(1,3)

CK2(1,3)

IOCA0

ICSPDAT

ICDDAT

RA16

ANA1

VREF+ (ADC)

DAC1REF0+

C1IN0-

C2IN0-

CLBIN2(1)CLCIN2(1)

SCL1(1,3)

SCK1(1,3)

RX1(1)

DT1(1,3)

RX2(1)

DT2(1,3)

IOCA1

ICSPCLK

ICDCLK

RA25ANA2DAC1OUT2T0CKI(1)

SDA1(1,3)

SDI1(1,3)

IOCA2INT(1)
RA34CLBIN0(1)CLCIN0 (1)SS1(1)IOCA3MCLR

VPP

RA43ANA4C1IN1-T1G(1)IOCA4

CLKOUT

OSC2

SOSCO

RA52

ANA5

ADACT(1)

T1CKI(1)

T2IN(1)

CCP1(1)

CCP2(1)

PWM1ERS(1)

CLBIN1(1)CLCIN1(1)IOCA5

CLKIN

OSC1

SOSCI

VDD1VDD
VSS8VSS
OUT(2)

ADGRDA

ADGRDB

CMP1

CMP2

TMR0

CCP1

CCP2

PWM11

PWM12

PWM21

PWM22

CLBPPSOUT0

CLBPPSOUT1

CLBPPSOUT2

CLBPPSOUT3

CLBPPSOUT4

CLBPPSOUT5

CLC1OUT

CLC2OUT

CLC3OUT

CLC4OUT

SCL1

SCK1

SDA1

SDO1

TX1

DT1

CK1

TX2

DT2

CK2

Note:
  1. This is a PPS remappable input signal. The input function may be moved from the default location shown to any PORTx pin.
  2. All output signals shown in this row are PPS remappable.
  3. This is a bidirectional signal. For normal operation, user software must map this signal to the same pin via the PPS input and PPS output registers.
Table . 14/16-Pin Allocation Table
I/O

14-Pin

SOIC

TSSOP

ADCDACComparatorTimersCCP

16-Bit

PWM

CLBCLC

I2C/

SPI

EUSARTIOCInterruptBasic
RA013ANA0DAC1OUT1C1IN0+IOCA0

ICSPDAT

ICDDAT

RA112

ANA1

VREF+(ADC)

DAC1REF0+

C1IN0-

C2IN0-

IOCA1

ICSPCLK

ICDCLK

RA211ANA2DAC1OUT2T0CKI(1)IOCA2INT(1)
RA34IOCA3MCLR

VPP

RA43ANA4T1G(1)IOCA4

CLKOUT

OSC2

SOSCO

RA52ANA5

T1CKI(1)

T2IN(1)

PWM1ERS(1)

CLBIN3(1)CLCIN3(1)IOCA5

CLKIN

OSC1

SOSCI

RC010ANC0C2IN0+SCL1(1,3,4)

SCK1(1,3,4)

CK2(1,3)IOCC0
RC19ANC1

C1IN1-

C2IN1-

T4IN(1)

PWM2ERS(1)

CLBIN2(1)CLCIN2(1)SDA1(1,3,4)

SDI1(1,3,4)

RX2(1)

DT2(1,3)

IOCC1
RC28

ANC2

ADACT(1)

C1IN2-

C2IN2-

IOCC2
RC37ANC3

C1IN3-

C2IN3-

CCP2(1)

PWMIN1(1)

CLBIN0(1)CLCIN0(1)SS1(1)IOCC3
RC46ANC4

T3G(1)

CLBIN1(1)CLCIN1(1)CK1(1,3)IOCC4
RC55ANC5

T3CKI(1)

CCP1(1)

PWMIN0(1)

RX1(1)

DT1(1,3)

IOCC5
VDD1VDD
VSS14VSS
OUT(2)

ADGRDA

ADGRDB

CMP1

CMP2

TMR0

CCP1

CCP2

PWM11

PWM12

PWM21

PWM22

CLBPPSOUT0

CLBPPSOUT1

CLBPPSOUT2

CLBPPSOUT3

CLBPPSOUT4

CLBPPSOUT5

CLBPPSOUT6

CLBPPSOUT7

CLC1OUT

CLC2OUT

CLC3OUT

CLC4OUT

SCL1

SCK1

SDA1

SDO1

TX1

DT1

CK1

TX2

DT2

CK2

Note:
  1. This is a PPS remappable input signal. The input function may be moved from the default location shown to any PORTx pin.
  2. All output signals shown in this row are PPS remappable.
  3. This is a bidirectional signal. For normal operation, user software must map this signal to the same pin via the PPS input and PPS output registers.
  4. These pins can be configured for I2C or SMBus logic levels via the RxyI2C registers. The SCL1/SDA1 signals may be assigned to these pins for expected operation. PPS assignments of these signals to other pins will operate; however, the logic levels will be standard TTL/ST as selected by the INLVL register.
Table . 20-Pin Allocation Table
I/O

20-Pin

PDIP

SSOP

20-Pin

VQFN

ADCDACComparatorTimersCCP

16-Bit

PWM

CLBCLC

I2C/

SPI

EUSARTIOCInterruptBasic
RA01916ANA0DAC1OUT1C1IN0+IOCA0

ICSPDAT

ICDDAT

RA11815

ANA1

VREF+(ADC)

DAC1REF0+

C1IN0-

C2IN0-

IOCA1

ICSPCLK

ICDCLK

RA21714ANA2DAC1OUT2T0CKI(1)CLBIN0(1)CLCIN0(1)IOCA2INT(1)
RA341IOCA3MCLR

VPP

RA4320ANA4T1G(1)IOCA4

CLKOUT

OSC2

SOSCO

RA5219ANA5

T1CKI(1)

T2IN(1)

PWM1ERS(1)IOCA5

CLKIN

OSC1

SOSCI

RB41310ANB4CLBIN2(1)CLCIN2(1)SDA1(1,3,4)

SDI1(1,3,4)

IOCB4
RB5129ANB5CLBIN3(1)CLCIN3(1)

RX1(1)

DT1(1,3)

IOCB5
RB6118ANB6SCL1(1,3,4)

SCK1(1,3,4)

IOCB6
RB7107ANB7CK1(1,3)IOCB7
RC01613ANC0C2IN0+CK2(1,3)IOCC0
RC11512ANC1

C1IN1-

C2IN1-

T4IN(1)

PWM2ERS(1)

RX2(1)

DT2(1,3)

IOCC1
RC21411

ANC2

ADACT(1)

C1IN2-

C2IN2-

IOCC2
RC374ANC3

C1IN3-

C2IN3-

CCP2(1)PWMIN1(1)CLBIN1(1)CLCIN1(1)IOCC3
RC463ANC4T3G(1)IOCC4
RC552ANC5T3CKI(1)CCP1(1)PWMIN0(1)IOCC5
RC685ANC6SS1(1)IOCC6
RC796ANC7IOCC7
VDD118VDD
VSS2017VSS
OUT(2)

ADGRDA

ADGRDB

CMP1

CMP2

TMR0

CCP1

CCP2

PWM11

PWM12

PWM21

PWM22

CLBPPSOUT0

CLBPPSOUT1

CLBPPSOUT2

CLBPPSOUT3

CLBPPSOUT4

CLBPPSOUT5

CLBPPSOUT6

CLBPPSOUT7

CLC1OUT

CLC2OUT

CLC3OUT

CLC4OUT

SCL1

SCK1

SDA1

SDO1

TX1

DT1

CK1

TX2

DT2

CK2

Note:
  1. This is a PPS remappable input signal. The input function may be moved from the default location shown to any PORTx pin.
  2. All output signals shown in this row are PPS remappable.
  3. This is a bidirectional signal. For normal operation, user software must map this signal to the same pin via the PPS input and PPS output registers.
  4. These pins can be configured for I2C or SMBus logic levels via the RxyI2C registers. The SCL1/SDA1 signals may be assigned to these pins for expected operation. PPS assignments of these signals to other pins will operate; however, the logic levels will be standard TTL/ST as selected by the INLVL register.
Table . 28-Pin Allocation Table
I/O

28-Pin

SSOP

28-Pin

VQFN

ADCDACComparatorTimersCCP

16-Bit

PWM

CLBCLC

I2C/

SPI

EUSARTIOCInterruptBasic
RA0227ANA0

C1IN0-

C2IN0-

CLCIN0(1)IOCA0
RA1328ANA1

C1IN1-

C2IN1-

CLCIN1(1)IOCA1
RA241ANA2DAC1OUT1

C1IN0+

C2IN0+

IOCA2
RA352ANA3

VREF+ (ADC)

DAC1REF0+C1IN1+IOCA3
RA463ANA4T0CKI(1)IOCA4
RA574ANA5SS1(1)IOCA5
RA6107ANA6IOCA6

CLKOUT

OSC2

RA796ANA7IOCA7

CLKIN

OSC1

RB02118ANB0C2IN1+SS2(1)IOCB0INT(1)
RB12219ANB1

C1IN3-

C2IN3-

SCL2(1,3,4)

SCK2(1,3,4)

IOCB1
RB22320ANB2

SDA2(1,3,4)

SDI2(1,3,4)

IOCB2
RB32421ANB3

C1IN2-

C2IN2-

IOCB3
RB42522

ANB4

ADACT(1)

IOCB4
RB52623ANB5T1G(1)IOCB5
RB62724ANB6CLCIN2(1)CK2(1,3)IOCB6

ICSPCLK

ICDCLK

RB72825ANB7DAC1OUT2CLCIN3(1)RX2(1)

DT2(1,3)

IOCB7

ICSPDAT

ICDDAT

RC0118ANC0T1CKI(1)

T3CKI(1)

T3G(1)

CLBIN0(1)IOCC0SOSCO
RC1129ANC1CCP2(1)PWMIN1(1)CLBIN1(1)IOCC1SOSCI
RC21310ANC2CCP1(1)PWMIN0(1)CLBIN2(1)IOCC2
RC31411ANC3T2IN(1)PWM1ERS(1)CLBIN3(1)

SCL1(1,3,4)

SCK1(1,3,4)

IOCC3
RC41512ANC4

SDA1(1,3,4)

SDI1(1,3,4)

IOCC4
RC51613ANC5T4IN(1)PWM2ERS(1)IOCC5
RC61714ANC6CK1(1,3)IOCC6
RC71815ANC7RX1(1)

DT1(1,3)

IOCC7
RE3126IOCE3MCLR

VPP

VDD2017VDD
VSS8

19

5

16

VSS
OUT(2)

ADGRDA

ADGRDB

CMP1

CMP2

TMR0

CCP1

CCP2

PWM11

PWM12

PWM21

PWM22

CLBPPSOUT0

CLBPPSOUT1

CLBPPSOUT2

CLBPPSOUT3

CLBPPSOUT4

CLBPPSOUT5

CLBPPSOUT6

CLBPPSOUT7

CLC1OUT

CLC2OUT

CLC3OUT

CLC4OUT

SCL1

SCK1

SDA1

SDO1

SCL2

SCK2

SDA2

SDO2

TX1

DT1

CK1

TX2

DT2

CK2

Note:
  1. This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to the PPS input table in the device data sheet for details on which PORT pins may be used for this signal.
  2. All output signals shown in this row are PPS remappable.
  3. This is a bidirectional signal. For normal operation, user software must map this signal to the same pin via the PPS input and PPS output registers.
  4. These pins can be configured for I2C or SMBus logic levels via the RxyI2C registers. The SCL1/SDA1 signals may be assigned to these pins for expected operation. PPS assignments of these signals to other pins will operate; however, the logic levels will be standard TTL/ST as selected by the INLVL register.
Table . 40/44-Pin Allocation Table
I/O

40-Pin

PDIP

40-Pin

VQFN

44-Pin

TQFP

ADCDACComparatorTimersCCP

16-Bit

PWM

CLBCLC

I2C/

SPI

EUSARTIOCInterruptBasic
RA021719ANA0

C1IN0-

C2IN0-

CLCIN0(1)IOCA0
RA131820ANA1

C1IN1-

C2IN1-

CLCIN1(1)IOCA1
RA241921ANA2DAC1OUT1

C1IN0+

C2IN0+

IOCA2
RA352022

ANA3

VREF+ (ADC)

DAC1REF0+C1IN1+IOCA3
RA462123ANA4T0CKI(1)IOCA4
RA572224ANA5SS1(1)IOCA5
RA6142931ANA6IOCA6

CLKOUT

OSC2

RA7132830ANA7IOCA7

CLKIN

OSC1

RB03388ANB0C2IN1+SS2(1)IOCB0INT(1)
RB13499ANB1

C1IN3-

C2IN3-

SCL2(1,3,4)

SCK2(1,3,4)

IOCB1
RB2351010ANB2

SDA2(1,3,4)

SDI2(1,3,4)

IOCB2
RB3361111ANB3

C1IN2-

C2IN2-

IOCB3
RB4371214

ANB4

ADACT(1)

IOCB4
RB5381315ANB5T1G(1)IOCB5
RB6391416ANB6CLCIN2(1)CK2(1,3)IOCB6

ICSPCLK

ICDCLK

RB7401517ANB7DAC1OUT2CLCIN3(1)

RX2(1)

DT2(1,3)

IOCB7

ICSPDAT

ICDDAT

RC0153032ANC0

T1CKI(1)

T3CKI(1)

T3G(1)

CLBIN0(1)IOCC0SOSCO
RC1163135ANC1CCP2(1)PWMIN1(1)CLBIN1(1)IOCC1SOSCI
RC2173236ANC2CCP1(1)PWMIN0(1)CLBIN2(1)IOCC2
RC3183337ANC3T2IN(1)PWM1ERS(1)CLBIN3(1)

SCL1(1,3,4)

SCK1(1,3,4)

IOCC3
RC4233842ANC4

SDA1(1,3,4)

SDI1(1,3,4)

IOCC4
RC5243943ANC5T4IN(1)PWM2ERS(1)IOCC5
RC6254044ANC6CK1(1,3)IOCC6
RC72611ANC7

RX1(1)

DT1(1,3)

IOCC7
RD0193438AND0
RD1203539AND1
RD2213640AND2
RD3223741AND3
RD42722AND4
RD52833AND5
RD62944AND6
RD73055AND7
RE082325ANE0
RE192426ANE1
RE2102527ANE2
RE311618IOCE3MCLR

VPP

VDD11

32

7

26

7

28

VDD
VSS12

31

6

27

6

29

VSS
OUT(2)

ADGRDA

ADGRDB

CMP1

CMP2

TMR0

CCP1

CCP2

PWM11

PWM12

PWM21

PWM22

CLBPPSOUT0

CLBPPSOUT1

CLBPPSOUT2

CLBPPSOUT3

CLBPPSOUT4

CLBPPSOUT5

CLBPPSOUT6

CLBPPSOUT7

CLC1OUT

CLC2OUT

CLC3OUT

CLC4OUT

SCL1

SCK1

SDA1

SDO1

SCL2

SCK2

SDA2

SDO2

TX1

DT1

CK1

TX2

DT2

CK2

Note:
  1. This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to the PPS input table in the device data sheet for details on which PORT pins may be used for this signal.
  2. All output signals shown in this row are PPS remappable.
  3. This is a bidirectional signal. For normal operation, user software must map this signal to the same pin via the PPS input and PPS output registers.
  4. These pins can be configured for I2C or SMBus logic levels via the RxyI2C registers. The SCL1/SDA1 signals may be assigned to these pins for expected operation. PPS assignments of these signals to other pins will operate; however, the logic levels will be standard TTL/ST as selected by the INLVL register.