3 Pin Allocation Tables

Table 3-1. 28-Pin Allocation Table
I/O28-Pin

SPDIP

SOIC

SSOP

28-Pin

VQFN

ADCReferenceComparatorZCDTimersCCPCWGCLCMSSPEUSARTIOCInterruptBasic
RA0227ANA0C1IN0-CLCIN0(1)IOCA0
RA1328ANA1C1IN1-CLCIN1(1)IOCA1
RA241ANA2DAC1REF0-C1IN0+IOCA2
RA352ANA3

DAC1REF0+

VREF+ (ADC)

C1IN1+IOCA3
RA463ANA4T0CKI(1)IOCA4
RA574ANA5SS1(1)IOCA5
RA6107ANA6IOCA6CLKOUT
RA796ANA7IOCA7CLKIN
RB02118ANB0ZCD1CWG1(1)SS2IOCB0INT(1)
RB12219ANB1C1IN3-SCL2(1,3,4)

SCK2(1,3,4)

IOCB1
RB22320ANB2SDA2(1,3,4)

SDI2(1,3,4)

IOCB2
RB32421ANB3C1IN2-IOCB3
RB42522ANB4

ADACT(1)

IOCB4
RB52623ANB5T1G(1)IOCB5
RB62724ANB6CLCIN2(1)CK2(1,3)IOCB6ICSPCLK

ICDCLK

RB72825ANB7DAC1OUT2T6IN(1)CLCIN3(1)RX2(1)

DT2(1,3)

IOCB7ICSPDAT

ICDDAT

RC0118ANC0T1CKI(1)

T3CKI(1)

T3G(1)

IOCC0SOSCO
RC1129ANC1CCP2(1)IOCC1SOSCI
RC21310ANC2CCP1(1)IOCC2
RC31411ANC3T2IN(1)SCL1(1,3,4)

SCK1(1,3,4)

IOCC3
RC41512ANC4SDA1(1,3,4)

SDI1(1,3,4)

IOCC4
RC51613ANC5T4IN(1)IOCC5
RC61714ANC6CK1(1,3)IOCC6
RC71815ANC7RX1(1)

DT1(1,3)

IOCC7
RE3126IOCE3MCLR

VPP

VDD2017VDD
VSS8

19

5

16

VSS
OUT(2)ADGRDA

ADGRDB

CMP1TMR0CCP1

CCP2

PWM3

PWM4

PWM5

CWG1A

CWG1B

CWG1C

CWG1D

CLC1OUT

CLC2OUT

CLC3OUT

CLC4OUT

SCL1

SCK1

SDA1

SDO1

SCL2

SCK2

SDA2

SDO2

TX1

DT1

CK1

TX2

DT2

CK2

Note:
  1. This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to the PPS input table in the device data sheet for details on which PORT pins may be used for this signal.
  2. All output signals shown in this row are PPS remappable.
  3. This is a bidirectional signal. For normal operation, user software must map this signal to the same pin via the PPS input and PPS output registers.
  4. These pins can be configured for I2C or SMBus logic levels via the RxyI2C registers. The SCL1/SDA1 signals may be assigned to these pins for expected operation. PPS assignments of these signals to other pins will operate; however, the logic levels will be standard TTL/ST as selected by the INLVL register.
Table 3-2. 40/44-Pin Allocation Table
I/O40-Pin

PDIP

40-Pin

QFN

44-Pin

TQFP

ADCReferenceComparatorZCDTimersCCPCWGCLCMSSPEUSARTIOCInterruptBasic
RA021719ANA0C1IN0-CLCIN0(1)IOCA0
RA131820ANA1C1IN1-CLCIN1(1)IOCA1
RA241921ANA2DAC1REF0-C1IN0+IOCA2
RA352022ANA3

DAC1REF0+

VREF+ (ADC)

C1IN1+IOCA3
RA462123ANA4T0CKI(1)IOCA4
RA572224ANA5SS1(1)IOCA5
RA6142931ANA6IOCA6CLKOUT
RA7132830ANA7IOCA7CLKIN
RB03388ANB0ZCD1CWG1(1)SS2(1)IOCB0INT(1)
RB13499ANB1C1IN3-SCL2(1,3,4)

SCK2(1,3,4)

IOCB1
RB2351010ANB2SDA2(1,3,4)

SDI2(1,3,4)

IOCB2
RB3361111ANB3C1IN2-IOCB3
RB4371214ANB4

ADACT(1)

IOCB4
RB5381315ANB5T1G(1)IOCB5
RB6391416ANB6CLCIN2(1)CK2(1,3)IOCB6ICSPCLK

ICDCLK

RB7401517ANB7DAC1OUT2T6IN(1)CLCIN3(1)RX2(1)

DT2(1,3)

IOCB7ICSPDAT

ICDDAT

RC0153032ANC0T1CKI(1)

T3CKI(1)

T3G(1)

IOCC0SOSCO
RC1163135ANC1CCP2(1)IOCC1SOSCI
RC2173236ANP2CCP1(1)IOCC2
RC3183337ANC3T2IN(1)SCL1(1,3,4)

SCK1(1,3,4)

IOCC3
RC4233842ANC4SDA1(1,3,4)

SDI1(1,3,4)

IOCC4
RC5243943ANC5T4IN(1)IOCC5
RC6254044ANC6CK1(1,3)IOCC6
RC72611ANC7RX1(1)

DT1(1,3)

IOCC7
RD0193438AND0
RD1203539AND1
RD2213640AND2
RD3223741AND3
RD42722AND4
RD52833AND5
RD62944AND6
RD73055AND7
RE082325ANE0IOCE0
RE192426ANE1IOCE1
RE2102527ANE2IOCE2
RE311618IOCE3MCLR

VPP

VDD11

32

7

26

7

28

VDD
VSS12

31

6

27

6

29

VSS
OUT(2)ADGRDA

ADGRDB

CMP1TMR0CCP1

CCP2

PWM3

PWM4

PWM5

CWG1A

CWG1B

CWG1C

CWG1D

CLC1OUT

CLC2OUT

CLC3OUT

CLC4OUT

SCL1

SCK1

SDA1

SDO1

SCL2

SCK2

SDA2

SDO2

TX1

DT1

CK1

TX2

DT2

CK2

Note:
  1. This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to the PPS input table in the device data sheet for details on which PORT pins may be used for this signal.
  2. All output signals shown in this row are PPS remappable.
  3. This is a bidirectional signal. For normal operation, user software must map this signal to the same pin via the PPS input and PPS output registers.
  4. These pins can be configured for I2C or SMBus logic levels via the RxyI2C registers. The SCL1/SDA1 signals may be assigned to these pins for expected operation. PPS assignments of these signals to other pins will operate; however, the logic levels will be standard TTL/ST as selected by the INLVL register.