30 EUSART - Enhanced Universal Synchronous Asynchronous Receiver Transmitter

The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is a serial I/O communications peripheral. It contains all the clock generators, shift registers and data buffers necessary to perform an input or output serial data transfer independent of device program execution. The EUSART, also known as a Serial Communications Interface (SCI), can be configured as a full-duplex asynchronous system or half-duplex synchronous system.

Full Duplex mode is useful for communications with peripheral systems, such as CRT terminals and personal computers. Half Duplex Synchronous mode is intended for communications with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs or other microcontrollers. These devices typically do not have internal clocks for baud rate generation and require the external clock signal provided by a host synchronous device.

The EUSART module includes the following capabilities:

  • Full-duplex asynchronous transmit and receive
  • Two-character input buffer
  • One-character output buffer
  • Programmable 8-bit or 9-bit character length
  • Address detection in 9-bit mode
  • Input buffer overrun error detection
  • Received character framing error detection
  • Half-duplex synchronous host
  • Half-duplex synchronous client
  • Programmable clock polarity in Synchronous modes
  • Sleep operation

The EUSART module implements the following additional features, making it ideally suited for use in Local Interconnect Network (LIN) bus systems:

  • Automatic detection and calibration of the baud rate
  • Wake-up on Break reception
  • 13-bit Break character transmit

Block diagrams of the EUSART transmitter and receiver are shown in Figure 30-1 and Figure 30-2.

The operation of the EUSART module consists of six registers:

  • Transmit Status and Control (TXxSTA)
  • Receive Status and Control (RCxSTA)
  • Baud Rate Control (BAUDxCON)
  • Baud Rate Value (SPxBRG)
  • Receive Data Register (RCxREG)
  • Transmit Data Register (TXxREG)

The RXx/DTx and TXx/CKx input pins are selected with the RXxPPS and TXxPPS registers, respectively. TXx, CKx, and DTx output pins are selected with each pin’s RxyPPS register. Since the RX input is coupled with the DT output in Synchronous mode, it is the user’s responsibility to select the same pin for both of these functions when operating in Synchronous mode. The EUSART control logic will control the data direction drivers automatically.

Figure 30-1. EUSART Transmit Block Diagram
Figure 30-2. EUSART Receive Block Diagram