HDL to Programming Flow

This section describes how the following steps are executed using Tcl.

As a best practice, the following resources are recommended in the top-level Tcl folder for building a Libero SoC project.

parameters.tcl: This Tcl file contains project variables as shown in the following snippet.
```
set prj_family     "PolarFire";
set prj_die        "MPF100T";
set prj_package    "FCG484";
set prj_speed      "-1";
set prj_root       "top";
```
Tip: Libero SoC tools profile can also be configured in parameters.tcl.
src: This folder contains all the required HDL, constraints, memory configuration, and stimulus source files required for a project.

design.tcl: This Tcl file imports all the HDL, constraints, memory configuration, and stimulus sources files. The following snippet shows a sample design.tcl.


import_files -hdl_source {./src/rtl_1.v} -library {work};
import_files -hdl_source {./src/rtl2.v} -library {work};
.
.
import_files -hdl_source {./src/top.v} -library {work};
import_files -sdc {./src/constraint/timing_user_constraints.sdc};
import_files -pdc {./src/constraint/io_constraints.pdc};
import_files -pdc {./src/constraint/fp_constraints.pdc};
import_files -stimulus {./src/stimulus/testbench_presynth.v} -library {stimulus};
import_files -stimulus {./src/stimulus/testbench_postsynth.v} -library {stimulus};
organize_tool_files -tool {SYNTHESIZE} \
 -file ./src/constraint/timing_user_constraints.sdc \
 -module {$prj_root} \
 -input_type {constraint}
organize_tool_files -tool {PLACEROUTE} \
 -file ./src/constraint/timing_user_constraints.sdc \
 -file ./src/constraint/io_constraints.pdc \
 -file ./src/constraint/fp_constraints.pdc \
 -module {$prj_root} \
 -input_type {constraint}
organize_tool_files -tool {VERIFYTIMING} \
 -file ./src/constraint/timing_user_constraints.sdc \
 -module {$prj_root} \
 -input_type {constraint}
organize_tool_files \ 
-tool {SIM_PRESYNTH} \
-file {./src/stimulus/testbench_presynth.v}

organize_tool_files \ 
-tool {SIM_POSTSYNTH} \
-file {./src/stimulus/testbench_postsynth.v}
configure_ram -cfg_file {./src/src_cfg/RAM.cfg}
configure_tool \
         -name {GENERATEPROGRAMMINGFILE} \
         -params {program_fabric:true} \
         -params {program_security:false} \
	 -params {sanitize_snvm:false}
associate_stimulus -file testbench.v -mode new -module stimulus

libero.tcl: This Tcl file executes the HDL to programming flow in Libero SoC.

Tip: In design.tcl, parameters for all Libero SoC tools can be configured using the configure_tool command. For more information, see Tcl Commands Reference Guide for Libero SoC Design Suite.