Transmit Buffer Register

The stand-alone I2C module has a dedicated transmit buffer register, I2CxTXB, which operates independently from the receive buffer. This differs from the MSSP module in that the MSSP module has only one buffer, SSPxBUF, to handle both transmit and receive functions.

The transmit buffer is loaded with a data byte (or client address when ABD = 1) that is to be shifted into the transmit shift register and transmitted onto the bus. When the I2CxTXB is empty, the Transmit Buffer Empty (TXBE) Status bit is set, allowing user software to load another byte into the buffer. Once the data is transmitted from the I2CxTXB register, the TXBE bit is cleared. If user software attempts to load the I2CxTXB while it is full, the Transmit Write Error (TXRE) Flag bit is set, a NACK is generated, and the new data is ignored. If the TXRE flag is set, software must clear this bit before attempting to load the buffer again. Additionally, setting the Clear Buffer (CLRBF) bit clears both the transmit and receive buffers, as well as the Transmit Interrupt Flag (TXIF) bit and Receive Interrupt Flag (RXIF) bit.