63.9.9 TWI Register Write Protection

The FLEXCOM operating mode (FLEX_MR.OPMODE) must be set to FLEX_MR_OPMODE_TWI to enable access to the write protection registers.

To prevent any single software error from corrupting TWI behavior, certain registers in the address space can be write-protected by setting the WPEN (Write Protection Enable), WPITEN (Write Protection Interrupt Enable), and/or WPCREN (Write Protection Control Enable) bits in the TWI Write Protection Mode Register (FLEX_TWI_WPMR).

If a write access to a write-protected register is detected, the Write Protection Violation Status (WPVS) flag in the TWI Write Protection Status Register (FLEX_TWI_WPSR) is set and the Write Protection Violation Source (WPVSRC) field indicates the register in which the write access has been attempted.

The WPVS bit is automatically cleared after reading FLEX_TWI_WPSR.

The following register(s) can be write-protected when WPEN is set:

• TWI Client Mode Register
• TWI Clock Waveform Generator Register
• TWI SMBus Timing Register
• TWI Matching Register
• TWI FIFO Mode Register

The following register(s) can be write-protected when WPITEN is set:

• TWI Interrupt Enable Register
• TWI Interrupt Disable Register

The following register(s) can be write-protected when WPCREN is set:

• TWI Control Register