63.10.57 TWI Client Mode Register
This register can only be written if the WPEN bit is cleared in the TWI Write Protection Mode Register.
| Name: | FLEX_TWI_SMR |
| Offset: | 0x608 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| DATAMEN | SADR3EN | SADR2EN | SADR1EN | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| SADR[6:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| MASK[6:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SNIFF | SCLWSDIS | BSEL | SADAT | SMHH | SMDA | NACKEN | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 31 – DATAMEN Data Matching Enable
| Value | Description |
|---|---|
| 0 | Data matching on first received data is disabled. |
| 1 | Data matching on first received data is enabled. |
Bit 30 – SADR3EN Client Address 3 Enable
| Value | Description |
|---|---|
| 0 | Client address 3 matching is disabled. |
| 1 | Client address 3 matching is enabled. |
Bit 29 – SADR2EN Client Address 2 Enable
| Value | Description |
|---|---|
| 0 | Client address 2 matching is disabled. |
| 1 | Client address 2 matching is enabled. |
Bit 28 – SADR1EN Client Address 1 Enable
| Value | Description |
|---|---|
| 0 | Client address 1 matching is disabled. |
| 1 | Client address 1 matching is enabled. |
Bits 22:16 – SADR[6:0] Client Address
The client device address is used in Client mode in order to be accessed by host devices in Read or Write mode.
SADR must be programmed before enabling Client mode or after a general call. Writes at other times have no effect.
Bits 14:8 – MASK[6:0] Client Address Mask
A mask can be applied on the client device address in Client mode in order to allow multiple address answer. For each bit of the MASK field set to one, the corresponding SADR bit will be masked.
If the MASK field is set to 0, no mask is applied to the SADR field.
Bit 7 – SNIFF Client Sniffer Mode
| Value | Description |
|---|---|
| 0 | Client Sniffer mode is disabled. |
| 1 | Client Sniffer mode is enabled. |
Bit 6 – SCLWSDIS Clock Wait State Disable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Clock stretching disabled in Client mode, OVRE and UNRE will indicate overrun and underrun. |
Bit 5 – BSEL TWI Bus Selection
| Value | Description |
|---|---|
| 0 |
TWI analyzes the TWCK and TWD pins from its TWI bus. |
| 1 | TWIn analyzes the TWCK and TWD pins of the peripheral TWIn+1 (TWImax analyzes TWI0). |
Bit 4 – SADAT Client Address Treated as Data
| Value | Description |
|---|---|
| 0 |
Client address is handled normally (will not trig RXRDY flag and will not fill FLEX_TWI_RHR upon reception). |
| 1 |
Client address is handled as data field, RXRDY will be set and FLEX_TWI_RHR filled upon client address reception. |
Bit 3 – SMHH SMBus Host Header
| Value | Description |
|---|---|
| 0 | Acknowledge of the SMBus Host Header disabled. |
| 1 | Acknowledge of the SMBus Host Header enabled. |
Bit 2 – SMDA SMBus Default Address
| Value | Description |
|---|---|
| 0 | Acknowledge of the SMBus Default Address disabled. |
| 1 | Acknowledge of the SMBus Default Address enabled. |
Bit 0 – NACKEN Client Receiver Data Phase NACK Enable
| Value | Description |
|---|---|
| 0 | Normal value to be returned in the ACK cycle of the data phase in Client Receiver mode. |
| 1 | NACK value to be returned in the ACK cycle of the data phase in Client Receiver mode. |