35.6 Main System Bus Clock Controller

The Main System Bus Clock Controller provides the main system bus clocks (MCKx) of the different peripheral groups, with the exception of MCK0 that is generated by the Processor Clock Controller and MCK2 that is hard-wired to DDRPLLCK. MCKx are the source clocks of the peripheral clocks. Each peripheral clock is generated by one MCKx. To know which peripherals are clocked by a specific MCKx, refer to the Peripheral Identifiers table in the section "System Interconnect and Security (SIS)".

When configuring an MCKx, it is mandatory to write PMC_MCR.CMD to ‘1’ and PMC_MCR.ID with the index of the corresponding MCKx.

To read the current configuration of an MCKx, PMC_MCR must be first accessed with PMC_MCR.CMD written to ‘0’ and PMC_MCR.PID field written with the index of the corresponding MCKx. This write does not modify the configuration of the peripheral. The PMC_MCR can then be read to know the configuration status of the corresponding PID.

The clock selection is done in PMC_MCR.CSS.

The prescaler is configured in PMC_MCR.PRES.

Each time PMC_MCR.CSS is configured to define a new MCKx, PMC_SR.MCKXRDY is cleared. It reads ‘0’ until all MCKx are established. Then, MCKXRDY is set and can trigger an interrupt to the processor.

PMC_MCR must not be written while the PMC_SR.MCKXRDY flag is low.