39.7.6 ACC Interrupt Status Register
| Name: | ACC_ISR |
| Offset: | 0x30 |
| Reset: | 0x80000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| MASK | |||||||||
| Access | R | ||||||||
| Reset | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SCO | CE | ||||||||
| Access | R | R | |||||||
| Reset | 0 | 0 |
Bit 31 – MASK Flag Mask
| Value | Description |
|---|---|
| 0 |
The CE flag and SCO value are valid. |
| 1 |
The CE flag and SCO value are invalid. |
Bit 1 – SCO Synchronized Comparator Output
Returns an image of the analog comparator output after being preprocessed (see Block Diagram).
If INV = 0
- SCO = 0 if inn > inp
- SCO = 1 if inp > inn
If INV = 1
- SCO = 1 if inn > inp
- SCO = 0 if inp > inn
Bit 0 – CE Comparison Edge (cleared on read)
| Value | Description |
|---|---|
| 0 |
No edge occurred (defined by EDGETYP) on analog comparator output since the last read of ACC_ISR. |
| 1 |
A selected edge (defined by EDGETYP) on analog comparator output occurred since the last read of ACC_ISR. |