39.7.2 ACC Mode Register

This register can only be written if the WPEN bit is cleared in the ACC Write Protection Mode Register.

Name: ACC_MR
Offset: 0x04
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
  FESELFSINV EDGETYP[1:0]ACEN 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 
Bit 76543210 
  SELPLUS[2:0] SELMINUS[2:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 

Bit 14 – FE Fault Enable

ValueNameDescription
0 DIS

The FAULT output is tied to 0.

1 EN

The FAULT output is driven by the signal defined by SELFS.

Bit 13 – SELFS Selection Of Fault Source

ValueNameDescription
0 CE

The CE flag is used to drive the FAULT output.

1 OUTPUT

The output of the analog comparator flag is used to drive the FAULT output.

Bit 12 – INV Invert Comparator Output

ValueNameDescription
0 DIS

Analog comparator output is directly processed.

1 EN

Analog comparator output is inverted prior to being processed.

Bits 10:9 – EDGETYP[1:0] Edge Type

ValueNameDescription
0 RISING

Only rising edge of comparator output

1 FALLING

Falling edge of comparator output

2 ANY

Any edge of comparator output

Bit 8 – ACEN Analog Comparator Enable

ValueNameDescription
0 DIS

Analog comparator disabled.

1 EN

Analog comparator enabled.

Bits 6:4 – SELPLUS[2:0] Selection For Plus Comparator Input

0..3: Selects the input to apply on analog comparator SELPLUS comparison input.

ValueNameDescription
0 ACC_INP0

Selects ACC_INP0

1 ACC_INP1

Selects ACC_INP1

2 ACC_INP2

Selects ACC_INP2

3 ACC_INP3

Selects ACC_INP3

Bits 2:0 – SELMINUS[2:0] Selection for Minus Comparator Input

0..3: Selects the input to apply on analog comparator SELMINUS comparison input.

ValueNameDescription
0 VBG

Selects VBG

1 ACC_INN1

Selects ACC_INN1

2 ACC_INN2

Selects ACC_INN2

3 ACC_INN3

Selects ACC_INN3