9.1 Description

The high-performance, low-power Arm Cortex-A7 processor features an L1 cache subsystem that provides full virtual memory capabilities. The Cortex-A7 processor implements the Arm v7-A architecture and runs 32-bit Arm instructions, and 16-bit and 32-bit Thumb instructions.

The Cortex-A7 Arm Neon Media Processing Engine (MPE) extends the Cortex-A7 functionality to provide support for the Arm v7 Advanced SIMD v2 and Vector Floating-Point v4 (VFPv4) instruction sets. The Cortex-A7 Neon MPE provides flexible and powerful acceleration for signal processing algorithms including multimedia such as image processing, video decode/encode, 2D/3D graphics, and audio. For details, refer to the Cortex-A7 Neon Media Processing Engine Technical Reference Manual.

The Cortex-A7 processor includes TrustZone technology to enhance security by partitioning the SoC’s hardware and software resources in a Secure world for the security subsystem and a Normal world for the rest, enabling a strong security perimeter to be built between the two. For details, refer to Security Extensions Overview in the Cortex-A7 Technical Reference Manual. Refer to the Arm Architecture Reference Manual, Arm v7-A and Arm v7-R edition for details on how TrustZone works in the architecture.

The Cortex-A7 core, the Floating Point Unit (FPU) and Neon Media Processing Engine (MPE) are based on Arm Ltd. r0p5 and are highly configurable at the hardware design stage. These configurations are described in the sections that follow. The default software configuration has been intensively tested and leads to best results in any conditions.