9.8 Performance Monitoring Unit (PMU)

The processor features a Performance Monitoring Unit (PMU), made up of logic to gather various statistics on the operation of the processor and memory system during runtime, based on the PMUv2 architecture. These events provide useful information about the behavior of the processor that can be used when debugging or profiling code.

The PMU provides four counters. Each counter can count any of the events available in the processor.

Refer to the Cortex-A7 Core Technical Reference Manual for details on the PMU extensions.