69.3.1 Clocks

The device features three USB 2.0 PHYs and each one has its own PLL. Each PLL is fed with the main crystal oscillator. The PLL starts as soon as PHY reset is released in RSTC_GRSTR.USB_RSTx. There is no control in the Power Management Controller (PMC). Refer to the section Electrical Characteristics.

The TCPC is clocked through the PMC. First configure the PMC to enable the TCPC peripheral clock (MCK1) and the TCPC 32 kHz generic clock (GCLK).

UHP12M, UHP48M and OHCI clocks are generated from Transceiver A so, for OHCI operations, Port A must be enabled.

If the USB port is suspended, the clocks to the UTMI of that port are stopped. As Port A UTMI controls the UTMI clocks for Ports B and C, stopping the UTMI clocks on Port A also prevents Ports B and C UTMIs from being clocked.

Clearing the SFR_UTMI0Rx.COMMONONN bit for each port prevents the USB suspend from stopping the UTMI clocks for that port.

To clear COMMONONN:
  1. Reset the USB port (by setting RSTC_GRSTR.USB_RSTx).
  2. Clear the COMMONONN bit.
  3. Release the USB port reset (by clearing USB_RSTx).
Note: At product start-up, if no bootable code is available to the product, by default Port A is configured in USB Device mode and suspended.
To enable access to Ports B and C programming interfaces, take Port A out of the USB Suspend state, either by:
  • disabling the USB Device mode on Port A by clearing UDPHS_CTRL.EN_UDPHS, or by
  • clearing the COMMONONN bit as described above.