45.6.13 Interrupts

An I2SMCC interrupt request can be triggered whenever one or several of the following bits are set in I2SMCC_ISRA and/or I2SMCC_ISRB:

  • Receive Left x Ready (RXLRDYx)
  • Receive Right x Ready (RXRRDYx)
  • Receive Left x Overrun (RXLOVFx)
  • Receive Right x Overrun (RXROVFx)
  • Transmit Left x Ready (TXLRDYx)
  • Transmit Right x Ready (TXRRDYx)
  • Transmit Left x Underrun (TXLUNFx)
  • Transmit Right x Underrun (TXRUNFx)
  • Write Error (WERR)
  • Transmit FIFO Ready (TXFFRDY)
  • Transmit FIFO Empty (TXFFEMP)
  • Receive FIFO Ready (RXFFRDY)
  • Receive FIFO Full (RXFFFUL)

The interrupt request is generated if the corresponding bit in the Interrupt Mask registers (I2SMCC_IMRA and I2SMCC_IMRB) is set. Bits in I2SMCC_IMRx are set by writing a ’1’ to the corresponding bit in I2SMCC_IERx and cleared by writing a ’1’ to the corresponding bit in I2SMCC_IDRx. The interrupt request remains active until the corresponding bit in I2SMCC_ISRx is cleared.

Figure 45-8. Interrupt Block Diagram