45.6.10 Holding Registers

The I2SMCC user interface includes two common holding registers—the Receive Holding Register (I2SMCC_RHR) and the Transmit Holding Register (I2SMCC_THR)— and dedicated holding registers per IO—the Receive Holding Left x Registers (I2SMCC_RHLxR), the Receive Holding Right x Registers (I2SMCC_RHRxR), the Transmit Holding Left x Registers (I2SMCC_THLxR) and the Transmit Holding Right x Registers (I2SMCC_THRxR). The common registers are used to access audio samples for all audio channels; the dedicated registers are used to access audio samples of one specific channel.

Access through common registers and dedicated registers must not be mixed. Only common registers or dedicated registers must be used.

The I2SMCC includes a Transmit (TX) FIFO and a Receive (RX) FIFO. Both FIFOs are only available through the common registers and must be enabled by setting FIFOEN in the Mode register B (I2SMCC_MRB). When FIFOs are enabled, I2SMCC_ISRA.TXLRDYx and I2SMCC_ISRA.TXRRDYx must not be used. TXFFRDY, TXFFEMP, RXFFRDY and RXFFFUL of the Interrupt Status register B (I2SMCC_ISRB) register provide the status of the FIFOs. These status bits are only available if FIFOEN is set.

Each I²S or TDM channel has its own register. The register depth depending on the configuration is available in the following table.