72.6.3 USB Transfer Event Definitions

A transfer is composed of one or several transactions as shown in the table below.

Table 72-2. USB Transfer Events
Transfer Transaction
Direction Type
CONTROL (bidirectional) Control Transfer (1)
  • Setup transaction → Data IN transactions → Status OUT transaction
  • Setup transaction → Data OUT transactions → Status IN transaction
  • Setup transaction → Status IN transaction
IN (device toward host) Bulk IN Transfer
  • Data IN transaction → Data IN transaction
Interrupt IN Transfer
  • Data IN transaction → Data IN transaction
Isochronous IN Transfer (2)
  • Data IN transaction → Data IN transaction
OUT (host toward device) Bulk OUT Transfer
  • Data OUT transaction → Data OUT transaction
Interrupt OUT Transfer
  • Data OUT transaction → Data OUT transaction
Isochronous OUT Transfer (2)
  • Data OUT transaction → Data OUT transaction
Note:
  1. Control transfer must use endpoints with one bank and can be aborted using a stall handshake.
  2. Isochronous transfers must use endpoints configured with two or three banks.

An endpoint handles all transactions related to the type of transfer for which it has been configured.

Table 72-3. UDPHS Endpoint Description
Endpoint # Mnemonic Nb Banks DMA High Bandwidth Max. Endpoint Size Endpoint Type
0 EPT_0 1 N N 64 Control
1 EPT_1 3 Y Y 1024 Ctrl/Bulk/Iso(1)/Interrupt
2 EPT_2 3 Y Y 1024 Ctrl/Bulk/Iso(1)/Interrupt
3 EPT_3 2 Y N 1024 Ctrl/Bulk/Iso(1)/Interrupt
4 EPT_4 2 Y N 512 Ctrl/Bulk/Iso(1)/Interrupt
5 EPT_5 2 Y N 512 Ctrl/Bulk/Iso(1)/Interrupt
6 EPT_6 2 Y N 512 Ctrl/Bulk/Iso(1)/Interrupt
7 EPT_7 2 Y N 512 Ctrl/Bulk/Iso(1)/Interrupt
8 EPT_8 1 N N 512 Ctrl/Bulk/Iso(1)/Interrupt
9 EPT_9 1 N N 512 Ctrl/Bulk/Iso(1)/Interrupt
10 EPT_10 1 N N 512 Ctrl/Bulk/Iso(1)/Interrupt
11 EPT_11 1 N N 512 Ctrl/Bulk/Iso(1)/Interrupt
12 EPT_12 1 N N 512 Ctrl/Bulk/Iso(1)/Interrupt
13 EPT_13 1 N N 512 Ctrl/Bulk/Iso(1)/Interrupt
14 EPT_14 1 N N 512 Ctrl/Bulk/Iso(1)/Interrupt
15 EPT_15 1 N N 512 Ctrl/Bulk/Iso(1)/Interrupt
Note:
  1. In Isochronous (Iso) mode, it is preferable that the high bandwidth capability is available.

The size of the internal DPRAM is 16448 bytes, covering the memory need for the seven endpoints, hence enabling static allocation of the memory for all endpoints.

Suspend and resume are automatically detected by the UDPHS device, which notifies the processor by raising an interrupt.