13.1 Description

The system embeds one AHB bus matrix.

This section describes how to perform priority, arbitration and security settings for peripherals indicated as “MATRIX” in the table “System Interconnections”. These include memories (USB_RAM, SRAM_P0, SRAM_P1, SMC, QSPI0, QSPI1, NFC_RAM) and ISC Host.

Refer to the section System Interconnect and Security (SIS) for the description of hosts, clients and interconnections.