22.3.2 GPBR Full Clear Register

This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode register (SYSC_WPMR).

Name: GPBR_FCLR
Offset: 0x04
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
        FCLR 
Access R/W 
Reset 0 

Bit 0 – FCLR Full Clear Enable

GPBR full clear is only possible if the system is not in Backup mode. In Backup mode, FCLR has no effect.
ValueDescription
0 SYS_GPBR0 is immediately cleared in case of fast wake-up pin tamper event.
1 SYS_GPBR0 and SYS_GPBR1 are immediately cleared in case of fast wake-up pin tamper event.