49.6.5 Receive Channel

Converted data are first written into a FIFO, then read in the Receive Holding register (PDMC_RHR) register. Active channel conversion results are sent to PDMC_RHR in a cyclic way. This means that the enabled channel with the lowest index is sent first, followed by the other enabled channels, increasing the index at each step. Once the enabled channel with the highest index is sent, the next conversion result of the enabled channel with the lowest index is sent, etc.

When at least one data is ready in the RX FIFO, the RXRDY flag rises and remains high as long as there is at least one data to be read in the FIFO.

When the entire FIFO has been filled with data (the FIFO has a depth of 16), the RXFULL flag rises. If new data is written into the RX FIFO while RXFULL is high, then the RXOVR flag rises. This flag remains high until the Interrupt Status register (PDMC_ISR) register is read.

Once all data contained in the RX FIFO are read, the RXEMPTY flag rises. If a data is read while the RX FIFO is empty, an underrun occurs and the RXUDR flag rises. This flag remains high until the PDMC_ISR register is read.

When a data is written in the RX FIFO, the RXRDY flag rises. If the corresponding interrupt has been enabled, an interrupt is generated and remains high as long as some data is available in the RX FIFO.

The receive FIFO circuitry features DMA chunk size management. The PDMC can be configured to optimize the number of trigger events sent to the DMA.

When the number of audio data samples equals the chunk size configured in PDMC_MR.CHUNK, the RXCHUNK flag rises and a trigger event is sent to DMA. The flag is reset once CHUNK data are read.