15.3.1 Clocks

Memory clocks are not controlled by the PMC.

ROM and CPKCC are on the CPU System and Security (CSS) matrix and therefore clocked by MCK0.
SECURAM is located on CSS and clocked by MCK0 divided by 32.
SRAM, SMC and NFC_RAM are located on the AHB System (HSS) matrix, clocked by MCK1.
UDDRC and DDR3PHY are clocked by MCK2 and hard-wired to the DDRPLLCK.

Note: The MCK0 frequency is directly related to the CPU clock, so any change on the CPU clock impacts MCK0.

CAUTION: MCK3 must be started during UDDRC and DDR3PHY initialization.

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